SiFive 0.7.0 Internal Release

What's Changed

• circt-reduce,firtool,llhd-sim: cleanup --help output, put options in category by @dtzSiFive in #2979
• [FIRRTL][Dedup] Improve error when module is both NoDedup and MustDedup by @youngar in #3032
• [FSM] Make initial state explicit by @mortbopet in #3019
• [FSM] Canonicalize away unreachable states by @mortbopet in #3020
• [FSM] Make transition guard and action regions optional by @mortbopet in #3021
• [ExportVerilog] Make isExpressionUnableToInline more liberal by @uenoku in #2974
• FIRParser: don't crash if no main module, print error by @dtzSiFive in #3035
• [CombFolds] Add a canonicalizer for andr, orr + replicate by @uenoku in #3038
• [FIRRTL] remove partialconnect by @dtzSiFive in #3027
• [HW] HWModuleGeneratedOp use SymbolUserOpInterface; LowerToHW use instanceGraph by @dtzSiFive in #3041
• [SCFToCalyx] Add source location metadata for Cider. by @cgyurgyik in #2959
• [FIRRTL] Add CheckResets Behavior to SFCCompat by @seldridge in #3049
• [Calyx] Implement ClkInsertion and ResetInsertion passes by @mortbopet in #3047
• [Handshake] Add tuple pack and unpack operations by @Dinistro in #3040
• [FIRRTL] Add ExtractInstances pass by @fabianschuiki in #3017
• [Calyx] Verify continuously assigned values by @mortbopet in #3048
• [Calyx] Factor out various helper functions by @mortbopet in #3055
• locationStyleInfo: add doc blurb, add to cl::opt help by @dtzSiFive in #3056
• FIRRTLFolds: don't crash on vector's connected to wire w/invalid by @dtzSiFive in #3044
• [LowerToHW][SVExtractTestCode] Don't extract assertions from testbench by @uenoku in #3058
• [FIRRTL] Look through tail/pad ops when checking for reset driver by @dtzSiFive in #3059
• ExportVerilog: Add lowering option to always print port direction/type by @dtzSiFive in #3046
• [FIRRTL] Move ExtractInstances pass before GCT by @prithayan in #3060
• Preserves FIRRTL names by @darthscsi in #3050
• [Calyx] Make wires op a graph region by @mortbopet in #3057
• [FIRRTL] Add error message to AnnotationArray type constraint by @youngar in #3061
• [FIRRTL] Fix module port insertion helper by @youngar in #3062
• [FIRRTL] Add FMemModule operation by @youngar in #3063
• [SV] Add a builder to CaseOp which takes a validation qualifier by @uenoku in #3075
• [FIRRTL] Add output-mlir option to firtool. by @mikeurbach in #3052
• [handshake-runner] Add support for tuple operations by @Dinistro in #3076
• [FIRRTL][InferWidths] Support bundles in mux constraint by @youngar in #3071
• [FIRRTL][FullAsyncResetTransform] Preseve synchronous reset value by @youngar in #3078
• LLVM bump (as we know it) by @drom in #3074
• [FIRRTL] Add AddSeqMemPorts pass by @youngar in #3064
• [FIRRTL] Add LowerMemory pass by @youngar in #3065
• [FIRRTL] Fix some passes to work with the new FMemModuleOp by @youngar in #3066
• [FIRRTL][PrefixModules] Prefix and duplicate FMemModule ops by @youngar in #3067
• [FIRRTL][LowerToHW] Lower firrtl.memmodule to hw.module.ext by @youngar in #3068
• [FIRRTL] Add the Mem to Registers transformation by @prithayan in #3039
• [ExportVerilog] Try to re-use existing inouts when possible. by @mikeurbach in #3080
• [FIRRTL][LowerMemory] Create wrapper module by @youngar in #3081
• Fix windows build by @youngar in #3082
• [FSM] Implement graph traits for fsm.machine by @mortbopet in #3073
• [FIRRTL] Track clock values of memory ports precisely by @uenoku in #3079
• Handle 0-length vectors in inferreset without connects to invalid by @darthscsi in #3083
• [ExportVerilog] Add parentheses around reduction ops by @uenoku in #3015

Full Changelog: sifive/0/6/0...sifive/0/7/0

Sifive 0.6.0 internal release

What's Changed

• [FIRRTL] [CheckCombCycle] Print a cycle while dumping signal names by @uenoku in #2942
• [Scheduling] Add consistency check. by @jopperm in #2953
• [Calyx] Update MultPipeOp and DivPipeOp format to round-trip. by @mikeurbach in #2954
• [Calyx] Add WireLibOp to represent a wire in Calyx's core library. by @mikeurbach in #2956
• [firtool] Apply CLI options to exportPm by @uenoku in #2961
• [FIRRTL] Do not dedup testharness memories by @prithayan in #2968
• [ExportVerilog] Fix an iterator update bug by @uenoku in #2964
• [ExportVerilog] Add a mechanism to control location info emission style by @uenoku in #2952
• [reduce] Add NodeSymbolRemover reduction by @uenoku in #2965
• WIP - Bump llvm. by @mikeurbach in #2969
• Revert "WIP - Bump llvm." by @mikeurbach in #2972
• Bump LLVM to 2d014b72ccb51de9a9627c31667a3edf8cca7616 (#2969) by @mikeurbach in #2973
• [FIRRTL] Omnibus fixes for Grand Central Signal Mappings by @seldridge in #2950
• [FIRRTL] Do not dedup testharness memory irrespective of Prefix by @prithayan in #2977
• Cmdline flags to deal with subcircuit by @darthscsi in #2981
• [FIRRTL] Make GroupID memory attribute unsigned. NFC by @prithayan in #2975
• [FIRRTL][Dedup] Fix MustDedup crash by @youngar in #2983
• [StandardToHandshake] Support external functions by @mortbopet in #2984
• [StandardToHandshake] Fix function type for external FuncOps by @mortbopet in #2987
• Update dialect overview diagram by @jopperm in #2976
• [FIRRTL] Add "_ext" suffix to Memory module and instance name by @prithayan in #2982
• [FIRRTL] Add a memory lowering pass by @prithayan in #2967
• [FIRRTL] Rename LowerMemory to FlattenMemory by @youngar in #2992
• [FIRRTL] Add documentation for AddSeqMemPort annotations by @youngar in #2993
• [FIRRTL] print mem.conf even if there are no memories by @youngar in #2991
• [FIRRTL][ModuleInliner] fix flatten+inline into multiple instance sites, annotation cleanup by @dtzSiFive in #2998
• [FIRRTL] [CheckCombCycles] Improve error message by reconstructing a full cycle by @uenoku in #2970
• [StandardToHandshake] enable reuse by exposing region lowering by @Dinistro in #2986
• [PyCDE] [NFC] Refactoring out the op caching code by @teqdruid in #3006
• [FIRRTL][LowerToHW] Insert extra initialization for async regs by @uenoku in #3000
• [MSFT] Make dynamic instances hierarchical by @teqdruid in #3005
• [PyCDE] [NFC] Rework instance hierarchy by @teqdruid in #3007
• [PyCDE] Teach PlacementDB how to resolve to Instances by @teqdruid in #3008
• [PyCDE] Adds support for rebuilding the instance cache by @teqdruid in #3011
• [Handshake] Make builders more flexible by using ValueRange by @Dinistro in #3013
• [SV] Avoid temporary wires when ReadInOutOp is after use by @nandor in #3009
• [Handshake] Improve handshake builders by @Dinistro in #3014
• [Handshake] Add optional visibility parsing for FuncOp by @Dinistro in #3016
• [FIRRTL] Add InjectDUTHierarchy Pass by @seldridge in #2989
• [Handshake] Add sink materialization for block arguments by @Dinistro in #3022
• [HW] Remove InstanceOp's constaint on the symbol by @youngar in #2994
• [HW] InnerNameRef backed by a symbol by @nandor in #2815
• [HW] Added a helper method to HWModuleOp to insert new outputs by @nandor in #2997
• FIREmitter: give strictconnect same invalid treatment, add test by @dtzSiFive in #3029
• [SV] Added macro.ref to reference macros. by @nandor in #2921
• FIRParser: fix ref invalidation in connectDebugInfo,emitPartialConnect by @dtzSiFive in #3026
• [FIRRTL] check flip orientation in connect operations by @dtzSiFive in #3025
• [FIRRTL] DUT seq mems paths should start from the DUT module. by @richardxia in #3031

New Contributors

• @dtzSiFive made their first contribution in #2998

Full Changelog: sifive/0/5/0...sifive/0/6/0

Sifive Internal 0.5.0

Sifive Internal Release

What's Changed

• [PyCDE] [ESI] Add ESI ports to PyCDE by @teqdruid in #2912
• [HW] Add a mutable specialization of SymbolCache by @mortbopet in #2919
• [HW] Add a parametric hw.module instance specialization pass by @mortbopet in #2882
• [Support] Make BackedgeBuilder use registered ops by @teqdruid in #2927
• Update LLVM submodule by @teqdruid in #2928
• [FIRRTL] Delete GCT taps that have no ports by @seldridge in #2934
• [SV] Add custom parser for case op for validation qualifier by @uenoku in #2930
• [FIRRTL] Handle zero bit Memory data fields by @prithayan in #2931
• [Comb] Removed range merging by @nandor in #2943
• [FIRRTL][ModuleInliner] Don't prefix memory names by @youngar in #2932
• [SV] Add a vendor extension "$deposit" by @darthscsi in #2936
• [Support] Backedges: Use always registered builtin.unrealized_conversion_cast by @teqdruid in #2948
• [FIRRTL] Drop GCT Signal Mapping 0-width targets by @seldridge in #2947
• [SV] Allow sv.wire in any non-procedural region. by @mikeurbach in #2949
• [FIRRTL] Grand Central Testharness Fixes by @seldridge in #2864

Full Changelog: sifive/0/4/0...sifive/0/5/0

Sifive Internal 0.4.0

Internal SiFive release.

What's Changed

• [cmake] Configure policy CMP0116 by @DeepFlyingSky in #2879
• Update LLVM to 3d4ca8a8c by @richardxia in #2886
• [RemoveInvalid] Support Aggregate by @uenoku in #2891
• [FIRRTL][Dedup] Fix incorrect string cast in printHash(). by @richardxia in #2895
• [FIRRTL] Fix RetimeModule Annotation. NFC. by @prithayan in #2897
• [FIRRTL][CheckCombCycles] Use FConnectLike by @uenoku in #2896
• [FIRRTL][Dedup] Directly use SHA256 byte array instead of converting to string. by @richardxia in #2894
• [FIRRTL] Donot dedup memories with unique Prefix by @prithayan in #2893
• [CI] Update nightly workflow to not fail fast. by @mikeurbach in #2899
• [firtool] Add --ir-sv flag by @nandor in #2902
• Update LLVM to 1aa4f0bb by @richardxia in #2901
• [FIRRTL] Set the GroupID at InferReadWrite pass. by @prithayan in #2917
• [SV] Add unique, priority constructs for case op by @uenoku in #2913
• [SV] Fix HWMemSimImpl Bad Randomization Verilog by @seldridge in #2906
• [FIRRTL][Dedup] enhance error messages for dedup failures by @youngar in #2887
• [FIRRTL] Remove Unused Instance Ports by @seldridge in #2852
• [SV] Skip extraction of bound instances by @seldridge in #2911
• [ExportVerilog] Add emitReplicatedOpsToHeader option by @uenoku in #2889
• [SV] Wrap IfDef conditions in a MacroIdentAttr by @nandor in #2904
• [firtool] Rerun CSE after canonicalization in HW/SV pipeline by @uenoku in #2918
• [HW] Add region-level definition initializer by @mortbopet in #2920
• [SV] Canonicalize empty IfDefProcedural op by @uenoku in #2924
• Move ifdef synthesis outside always block in firrtl lowering by @darthscsi in #2922
• [FIRParser] Fix partial connect expansion with analog in bundles by @youngar in #2925
• [PyCDE][NFC] Cleaning up Values and Types with new by @teqdruid in #2914

Full Changelog: sifive/0/3/0...sifive/0/4/0

SiFive 0.3.0

Weekly snapshot for SiFive use.

What's Changed

• Update LLVM by @prithayan in #2833
• [firtool] Print parsing time with verbose-pass-executions option by @uenoku in #2837
• Update LLVM by @trilorez in #2841
• [PyCDE] Infer the result type of a SystolicArray PE by @teqdruid in #2844
• [CI] Only build host backend in integration test by @uenoku in #2845
• [HW][FIRRTL] Added HWInstanceLike and HWModuleLike by @nandor in #2848
• [firtool] verbose-pass-execution should print the final passes. by @mikeurbach in #2855
• [FIRRTL] Relax reg reset width checking by @youngar in #2856
• [HW][FIRRTL] Factored out common instance graph construction to InstanceGraphBase by @nandor in #2849
• [llhd] Refactor struct Signal with class Signal by @DeepFlyingSky in #2829
• [HWMemSimImpl] Fix randomization of wide memories by @fabianschuiki in #2859
• [HW] Introduce hw::InstanceGraph based on InstanceGraphBase by @nandor in #2847
• [HWMemSimImpl] Randomize each memory word separately by @fabianschuiki in #2860
• [InferResets] Fix inference for zero-length vectors by @fabianschuiki in #2858
• [ExportVerilog] Removed redundant sv::IfOp inversion by @nandor in #2826
• [HW] Support parametric hw.arrays by @mortbopet in #2703
• [HW] Canonicalized integer interval tests by @nandor in #2748
• [NFC] Change Canonicalization pattern to avoid exponential behavior by @darthscsi in #2865
• Improve SV Case handling by @darthscsi in #2861
• [FIRRTL] [MergeConnection] Use StrictConnect by @uenoku in #2871
• [FIRParser] Create more precise timing scopes by @uenoku in #2875
• [FIRRTL][NFC] Introduce FConnectLike interface by @uenoku in #2872
• [NFC,FIRRTL] Use a symbol uses verifier for nla verification by @darthscsi in #2877
• [NFC] cache attr by @darthscsi in #2878
• [FIRRTL] Exposed utilities mapping paths to named operations by @nandor in #2862
• [Comb] Fix an edge case of the interval canonicalizer by @uenoku in #2880
• [FIRParser] Default chisel3 asserts to ifElseFatal by @youngar in #2876
• [Scheduling] Add an overview/rationale doc. by @jopperm in #2835
• [Comb] Fixed folding of whole interval checks in OrOp by @nandor in #2883
• [ExportVerilog] Inline StructExtract even with multiple uses by @uenoku in #2884
• [Docs] [CMake] Add install script for OR-Tools; mention it in Getting Started guide by @jopperm in #2868
• [ExportVerilog] Remove max token limit and spilling in ExportVerilog. by @mikeurbach in #2802
• [FIRRTL] s/RemoveResets/RemoveInvalid/ and Make All Invalids Zero by @seldridge in #2870

Full Changelog: sifive/0/2/0...sifive/0/3/0

Sifive 0.2.0

Weekly snapshot for Sifive use.

What's Changed

• [Tests] Added Icarus Verilog test harness by @nandor in #2739
• Track LLVM commits by @GeorgeLyon in #2801
• Update LLVM by @youngar in #2813
• [LLHD] Refactor enum class and move header file locations. by @DeepFlyingSky in #2805
• [Moore] Add concat expression by @fabianschuiki in #2799
• [FIRRTL] Use the new dutModuleName attribute for root of port target. by @mikeurbach in #2817
• [FIRRTL] Fix port symbol creation logic edge case in LowerTypes. by @mikeurbach in #2819
• [Support] Extract ValueMapper to separate support file by @mortbopet in #2725
• [LLHD] Refactor struct Time with class Time. by @DeepFlyingSky in #2814
• [Moore] Add shift expressions by @maerhart in #2812
• [SV] Use Better Named Wires When Possible by @seldridge in #2821
• [MSFT] Systolic Arrays -- high level model by @teqdruid in #2822
• [HW] Support hw.instance of modules with parametric in/out types by @mortbopet in #2823
• [ExportVerilog] Printed nested else-if ops as else if by @nandor in #2776
• [FIRRTL][HW] Added module visibility attributes by @nandor in #2816
• [Moore] Add types to C API by @maerhart in #2827
• [PyCDE] Add SystolicArray construct by @teqdruid in #2831
• [ExportVerilog] Make module portlist one name per line, more like humans often do. by @darthscsi in #2824
• [ExportVerilog] explicitBitcastAddMul all add/mul by @seldridge in #2832
• [FIRRTL][Dedup] Don't dump the circuit on errors by @youngar in #2834
• [FIRRTL][Dedup] Delay fixup of connects by @youngar in #2830

Full Changelog: sifive/0/1/0...sifive/0/2/0

SiFive-v0.1.0

This release covers accumulated bug fixes after the 0.0.9 release from running CIRCT on a matrix of internal designs.

What's Changed

• use hasVerifier instead of verifier by @DeepFlyingSky in #2775
• [FIRRTL][InstanceGraph] Add missing implementation of addModule() by @youngar in #2786
• Bump LLVM to 1ebf1afb4ff by @nandor in #2789
• [FIRRTL] Parse nonlocal annotations on ports correctly by @prithayan in #2792
• [NFC] Rename dump method with toString method by @DeepFlyingSky in #2797
• [HW] GlobalRefOp performance enhancement by @teqdruid in #2796
• [FIRRTL] Put Grand Central Black Boxes in Correct Directories by @seldridge in #2798
• [FIRRTL] Infer type of mux with aggregate operands by @fabianschuiki in #2807
• [FIRRTL] Cleaned up verifiers for connects by @nandor in #2765
• [FIRRTL] Verified types for RegOp and RegResetOp by @nandor in #2741
• [FIRParser] Expand and remove partial connects at parse time by @youngar in #2793
• [PrepareForEmission] Add max expression size before creating a wire. by @mikeurbach in #2795
• [ExportVerilog] Add explicit bitcast for width mismatch LINT errors by @prithayan in #2756
• [MSFT] [PyCDE] Make placement DB global rather than rooted by @teqdruid in #2804

Full Changelog: sifive/0/0/9...sifive/0/1/0

SiFive-v0.0.9

This release covers accumulated bug fixes after the 0.0.8 release from running CIRCT on a matrix of internal designs.

What's Changed

• [HandshakeToHW] Initial commit for handshake-to-hw by @mortbopet in #2680
• [Handshake] Generate dialect documentation #2677 by @mortbopet in #2697
• [LLHD] Fix SigArrayGetOp canonicalization by @maerhart in #2698
• Bump LLVM, Remove Duplicate Handshake Verification by @seldridge in #2702
• [PyCDE] Implement new DynamicInstance operation methodology by @teqdruid in #2683
• [Handshake] Make BufferOp sequential attribute a StrEnumAttr attribute by @DeepFlyingSky in #2670
• Add IDE configuration for CLion by @sequencer in #2679
• Add NLATable analysis and use it in PrefixModules by @darthscsi in #2695
• [FIRRTL][RemoveUnusedPorts] Support strictconnect by @uenoku in #2700
• [HW] Allow hw::IntType in hw::isHWIntegerType by @mortbopet in #2701
• [FIRRTL] Fix GCT Data Tap Bug by @seldridge in #2711
• [FIRRTL][Dedup] Fix issue with NLAs on ExtModule ports by @youngar in #2714
• [LowerToHW] Guard out-of-bounds multi-bit mux by @seldridge in #2716
• [reduce] Make reducer NLA aware by @fabianschuiki in #2715
• [FIRTL][Annotations] Fix issue when module name matches inner name by @youngar in #2717
• [FIRRTL][Dedup] Include port types in ext module hashing by @youngar in #2721
• [FIRRTL] Properly handle analog types w/ NamePreservation option by @youngar in #2723
• [Moore] Add SystemVerilog types by @fabianschuiki in #2699
• [HW] Add port dir flip function, make PortDirection an enum class; NFC by @fabianschuiki in #2726
• [Moore] Omit wrapper types where unique by @maerhart in #2729
• [FIRRTL] Add more tests for NamePreservation by @youngar in #2724
• [LowerToHW] Don't extract TestHarness verif bboxes by @seldridge in #2732
• [FIRRTL][Dedup] Get a module's name before deleting it by @youngar in #2734
• [FIRRTL][LowerTypes] Fix std::lower_bound usage by @youngar in #2736
• [FIRRTL][NLATable] Fix invalidated reference after growing a DenseMap by @youngar in #2738
• [FIRRTL][WireDFT] Fix invalidated reference from growing DenseMap by @youngar in #2735
• [FIRRTL][ExpandWhens] Improve location tracking while lowering by @youngar in #2742
• [SV] Add a File Descriptor parameter to FWriteOp by @nandor in #2737
• [LLHD] Process Lowering: support muxed signals by @maerhart in #2720
• [HandshakeToFIRRTL]: Add support for signed ops by @Dinistro in #2730
• [HW] Add port modification for module-like ops by @fabianschuiki in #2727
• [LLHD] Allow instantiation of hw.module by @maerhart in #2743
• [FIRRTL] Add signalPassFailure to LowerToHW and exit early. by @mikeurbach in #2745
• [FIRRTL] Don't lower types for invalid durring parsing. by @darthscsi in #2731
• [NFC] silence warning by @darthscsi in #2754
• InferReset generates strict connects by @darthscsi in #2753
• [FIRRTL][OMIR] Don't assume NLA's have an absolute path by @youngar in #2747
• [HW][ExportModuleHierarchy] Allow multiple output files per module by @youngar in #2752
• [LLHD] Add output operation by @maerhart in #2762
• Bump LLVM to 61814586 by @fabianschuiki in #2758
• [HWMemSimImpl] Add Memory Randomization by @seldridge in #2757
• [FIRRTL] Emitted PartialConnect instead of Connect for mismatched types by @nandor in #2764
• [FIRRTL] Fixed issue with undefined registers in HWMemSim by @nandor in #2769
• [FIRRTL][Inliner] Filter non-local annos by the instance path by @youngar in #2770
• [GCT] Create the proper XMR for GCT memtaps by @prithayan in #2771
• [HW] Add clog2 parameter expression by @trilorez in #2766
• [FIRRTL][Inliner] Fix NLA filtering on symbol collision by @youngar in #2777
• [FIRParser] Don't bulk connect bundles with analog in them by @youngar in #2778
• [Calyx] SCFToCalyx generates zero-width memref address ports for memrefs with size 1 dims by @makslevental in #2661
• [IMCONSTPROP] Only merge the reset value into a register if the enabl… by @darthscsi in #2780
• [InferReadWrite] Identify StrictConnectOp patterns along with ConnectOp by @prithayan in #2783
• [FIRRTL][LowerToHW] Find the DUT in a prepass by @youngar in #2784

New Contributors

• @nandor made their first contribution in #2737
• @Dinistro made their first contribution in #2730
• @makslevental made their first contribution in #2661

Full Changelog: sifive/0/0/8...sifive/0/0/9

Sifive 0.0.8 release

[FIRRTL] Preserve/Tap all "Named" Nodes or Wires (#2676)

Change end-to-end FIRRTL compilation behavior to preserve (via tapping) all
nodes and wires which are "named".  A "named" node or wire is one whose name
does not begin with an underscore.  Tapping is done by creating a "shadow node"
that is assigned the value of the actual wire and marked "don't touch".

This is done to enable better debug-ability of Chisel designs by enabling users
to always have references to named things they define in Chisel.  More
specifically, anytime a Chisel user defines a `val foo = <expression>`, CIRCT
will now produce a wire called "foo" in the output Verilog.

Add a parser option for controlling whether or not "named" wires and
nodes will be preserved from FIRRTL to Verilog.

Add a firtool command-line option for disabling name preservation during
FIRRTL parsing.

Signed-off-by: Schuyler Eldridge <[email protected]>

Sifive-v0.0.7

Internal Sifive release.