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SiFive-v0.0.9

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@seldridge seldridge released this 18 Mar 02:24
· 5227 commits to main since this release
sifive/0/0/9
3f934d4

This release covers accumulated bug fixes after the 0.0.8 release from running CIRCT on a matrix of internal designs.

What's Changed

  • [HandshakeToHW] Initial commit for handshake-to-hw by @mortbopet in #2680
  • [Handshake] Generate dialect documentation #2677 by @mortbopet in #2697
  • [LLHD] Fix SigArrayGetOp canonicalization by @maerhart in #2698
  • Bump LLVM, Remove Duplicate Handshake Verification by @seldridge in #2702
  • [PyCDE] Implement new DynamicInstance operation methodology by @teqdruid in #2683
  • [Handshake] Make BufferOp sequential attribute a StrEnumAttr attribute by @DeepFlyingSky in #2670
  • Add IDE configuration for CLion by @sequencer in #2679
  • Add NLATable analysis and use it in PrefixModules by @darthscsi in #2695
  • [FIRRTL][RemoveUnusedPorts] Support strictconnect by @uenoku in #2700
  • [HW] Allow hw::IntType in hw::isHWIntegerType by @mortbopet in #2701
  • [FIRRTL] Fix GCT Data Tap Bug by @seldridge in #2711
  • [FIRRTL][Dedup] Fix issue with NLAs on ExtModule ports by @youngar in #2714
  • [LowerToHW] Guard out-of-bounds multi-bit mux by @seldridge in #2716
  • [reduce] Make reducer NLA aware by @fabianschuiki in #2715
  • [FIRTL][Annotations] Fix issue when module name matches inner name by @youngar in #2717
  • [FIRRTL][Dedup] Include port types in ext module hashing by @youngar in #2721
  • [FIRRTL] Properly handle analog types w/ NamePreservation option by @youngar in #2723
  • [Moore] Add SystemVerilog types by @fabianschuiki in #2699
  • [HW] Add port dir flip function, make PortDirection an enum class; NFC by @fabianschuiki in #2726
  • [Moore] Omit wrapper types where unique by @maerhart in #2729
  • [FIRRTL] Add more tests for NamePreservation by @youngar in #2724
  • [LowerToHW] Don't extract TestHarness verif bboxes by @seldridge in #2732
  • [FIRRTL][Dedup] Get a module's name before deleting it by @youngar in #2734
  • [FIRRTL][LowerTypes] Fix std::lower_bound usage by @youngar in #2736
  • [FIRRTL][NLATable] Fix invalidated reference after growing a DenseMap by @youngar in #2738
  • [FIRRTL][WireDFT] Fix invalidated reference from growing DenseMap by @youngar in #2735
  • [FIRRTL][ExpandWhens] Improve location tracking while lowering by @youngar in #2742
  • [SV] Add a File Descriptor parameter to FWriteOp by @nandor in #2737
  • [LLHD] Process Lowering: support muxed signals by @maerhart in #2720
  • [HandshakeToFIRRTL]: Add support for signed ops by @Dinistro in #2730
  • [HW] Add port modification for module-like ops by @fabianschuiki in #2727
  • [LLHD] Allow instantiation of hw.module by @maerhart in #2743
  • [FIRRTL] Add signalPassFailure to LowerToHW and exit early. by @mikeurbach in #2745
  • [FIRRTL] Don't lower types for invalid durring parsing. by @darthscsi in #2731
  • [NFC] silence warning by @darthscsi in #2754
  • InferReset generates strict connects by @darthscsi in #2753
  • [FIRRTL][OMIR] Don't assume NLA's have an absolute path by @youngar in #2747
  • [HW][ExportModuleHierarchy] Allow multiple output files per module by @youngar in #2752
  • [LLHD] Add output operation by @maerhart in #2762
  • Bump LLVM to 61814586 by @fabianschuiki in #2758
  • [HWMemSimImpl] Add Memory Randomization by @seldridge in #2757
  • [FIRRTL] Emitted PartialConnect instead of Connect for mismatched types by @nandor in #2764
  • [FIRRTL] Fixed issue with undefined registers in HWMemSim by @nandor in #2769
  • [FIRRTL][Inliner] Filter non-local annos by the instance path by @youngar in #2770
  • [GCT] Create the proper XMR for GCT memtaps by @prithayan in #2771
  • [HW] Add clog2 parameter expression by @trilorez in #2766
  • [FIRRTL][Inliner] Fix NLA filtering on symbol collision by @youngar in #2777
  • [FIRParser] Don't bulk connect bundles with analog in them by @youngar in #2778
  • [Calyx] SCFToCalyx generates zero-width memref address ports for memrefs with size 1 dims by @makslevental in #2661
  • [IMCONSTPROP] Only merge the reset value into a register if the enabl… by @darthscsi in #2780
  • [InferReadWrite] Identify StrictConnectOp patterns along with ConnectOp by @prithayan in #2783
  • [FIRRTL][LowerToHW] Find the DUT in a prepass by @youngar in #2784

New Contributors

Full Changelog: sifive/0/0/8...sifive/0/0/9