firtool-1.89.0

What's Changed

• [Verif] Simplify the FormalOp by @fabianschuiki in #7691
• [Sim][NFC] Include InferTypeOpInterface in SimOps.td by @fabianschuiki in #7693
• [MooreToCore] Support assert, assume, cover ops by @mingzheTerapines in #7681
• [MooreToCore] Add support for format strings and display task by @fabianschuiki in #7694
• [ExtractInstances] Add the extract instances metadata to OM Classes by @prithayan in #7667
• [FIRRTL] collection of changes to InferWidths by @youngar in #7686
• [FIRRTL] InferWidths: fix invalid frame reference by @youngar in #7697
• [ArcToLLVM] Add support for index dialect by @fabianschuiki in #7699
• [Arc] Add arc.final op by @fabianschuiki in #7700
• [Arc] Make arc.model have an SSACFG region by @fabianschuiki in #7701
• Remove redundant CMakeLists.txt entry by @leonardt in #7696
• [FIRRTL][ProbesToSignals] RWProbe support by @dtzSiFive in #7706
• [Arc] Add dominance-aware pass to sink ops and merge scf.if ops by @fabianschuiki in #7702

Full Changelog: firtool-1.88.0...firtool-1.89.0

firtool-1.88.0

What's Changed

• [LLHD][HW] Implement SROA interfaces by @maerhart in #7672
• [FIRRTL] InferResets: properly lower FART'd registers by @youngar in #7680
• [OM] Update FreezePaths to handle object fields with paths. by @mikeurbach in #7683
• [JSON] Leave json::OStream in valid state on failure by @fabianschuiki in #7684
• Add unit test discovery and execution tool by @fabianschuiki in #7685
• [FIRRTL] Print port names attributes if a port has an empty name by @rwy7 in #7688
• [FIRRTL] Ensure LowerClasses respects alt base path for local paths. by @mikeurbach in #7690

Full Changelog: firtool-1.87.0...firtool-1.88.0

firtool-1.85.1

Full Changelog: firtool-1.85.0...firtool-1.85.1

firtool-1.87.0

What's Changed

• [FIRRTL] Make IMCP work with Layers by @seldridge in #7598
• [HW] Add reduction patterns to trim port list of top-level module by @maerhart in #7587
• [Arc] Fully support initialization through seq.initial by @uenoku in #7605
• [CMake] Consistently declare conversion libraries and simplify circt-opt link target list by @maerhart in #7610
• LLVM Bump by @maerhart in #7609
• [Moore] Add assert, assume, and cover ops. by @hailongSun2000 in #7589
• [FIRRTL] Allow local targets to be multiply-instantiated. by @mikeurbach in #7613
• [FIRRTL] Add InstanceInfo Analysis by @seldridge in #7612
• [LLHD][TCM] Simplify region directly by @maerhart in #7615
• [LLHD] Make process lowering best-effort and allow constants from outside the region by @maerhart in #7617
• [FIRRTL] Add features, cleanup InstanceInfo (again) by @seldridge in #7618
• Add verif.bmc VerifToSMT lowering by @TaoBi22 in #7603
• [SV] Add MacroRefOp to represet macro statement by @uenoku in #7607
• [MooreToCore] Alternative conditional lowering and type conversion fixes by @maerhart in #7625
• [circt-bmc] Add circt-bmc tool by @TaoBi22 in #7621
• [MooreToCore] Return early on non-convertable type by @maerhart in #7631
• [LLHD] Add DesequentializationPass by @maerhart in #7616
• [LLHD] Add Sig2Reg pass for graph regions by @maerhart in #7623
• [Moore] Drop named_constant op in favor of dbg.variable by @fabianschuiki in #7624
• [ImportVerilog] Add support for elaboration system tasks by @fabianschuiki in #7632
• [FIRRTL] Add verifier of single MarkDUTAnnotation by @seldridge in #7633
• [FIRRTL] Inliner: Support for ops with regions. by @dtzSiFive in #7398
• [firtool] Move LowerLayers later in pipeline. by @dtzSiFive in #7639
• [FIRRTL] Use walk, InstanceInfo in AddSeqMemPorts by @seldridge in #7599
• Bump LLVM to 556ec4a7261447d13703816cd3730a891441e52c. by @mikeurbach in #7641
• [ImportVerilog] Add support for $stop/$finish/$exit by @fabianschuiki in #7634
• [DC] Adding dc-print-dot pass by @luisacicolini in #7619
• [FIRRTL] Avoid InstanceGraphNode* in InstanceInfo by @seldridge in #7643
• [ImportVerilog] Add $display/$write/$info/$warning/$error/$fatal by @fabianschuiki in #7642
• [ImportVerilog] Add support for $clog2 by @fabianschuiki in #7645
• [FIRRTL] Error mixed DUT mems in AddSeqMemPorts by @seldridge in #7622
• [ImportVerilog] Support assignment patterns with integer type by @fabianschuiki in #7646
• [ImportVerilog] Insert missing conversions around instance ports by @fabianschuiki in #7647
• [FIRRTL][LowerLayers] Remove handling of some ref ops by @rwy7 in #7640
• [Analysis] Add OpCount Analysis by @TaoBi22 in #7644
• [Arc] Fix folding of initialized StateOp by @fzi-hielscher in #7653
• [Transforms][OpCountAnalysis] Add PrintOpCountPass by @TaoBi22 in #7654
• [MooreToCore] Lower moore.net to llhd.sig by @fabianschuiki in #7652
• [FIRRTL] Re-implement old EmitOMIR ports logic in LowerClasses. by @mikeurbach in #7651
• [Seq][Arc] Allow seq.initial to take immutable operands. Add a cast operation by @uenoku in #7656
• [FIRRTL] Add integer shift left property op by @maerhart in #7657
• [arcilator] Register Verif dialect by @owlxiao in #7655
• [OM] Add integer shift left op by @maerhart in #7658
• [FIRRTL] Add integer shift left parser support by @maerhart in #7659
• [FIRRTL] Add integer shift left conversion to LowerClasses by @maerhart in #7660

New Contributors

• @owlxiao made their first contribution in #7655

Full Changelog: firtool-1.86.0...firtool-1.87.0

firtool-1.86.0

What's Changed

• [FIRRTL][FIRParser] Check force source more. by @dtzSiFive in #7574
• Make sure type conversion materialization callbacks return values of the correct type by @maerhart in #7583
• Bump LLVM by @maerhart in #7572
• [python] Add walk_with_filter to walk subset of IR by @uenoku in #7591
• [FIRRTL][GrandCentral] Remove legacy Augmented types. by @dtzSiFive in #7592
• [python] Fix clang-tidy warnings in walk_with_filter, NFC by @uenoku in #7594
• [FIRRTL] Convert LowerMemory to walk by @seldridge in #7596
• LLVM Bump by @maerhart in #7595
• [FIRRTL] Change InferReadWrite to use a walk, error if it sees WhenOps by @seldridge in #7597

Full Changelog: firtool-1.85.0...firtool-1.86.0

firtool-1.62.1

What's Changed

• [FIRRTL] LowerToHW: guard against folded operations (#7358) (backport) by @dtzSiFive in #7590

Full Changelog: firtool-1.62.0...firtool-1.62.1

firtool-1.85.0

What's Changed

• [Seq] Introduce seq.initial, !seq.immutable and replace powerOn value with initial value in compreg by @uenoku in #7553
• [ESI] Add optional non-blocking write API to WriteChannelPort by @mortbopet in #7555
• [ESI][Runtime] Pretty printing of service ports by @teqdruid in #7567
• Bump LLVM to 10407be542aeb2b59477b167bbba3716538dc722. by @mikeurbach in #7550
• [ESI][Runtime] Address MMIO regions symbolically by @teqdruid in #7568
• [ESI] Don't assume using namespace std in Manifest.cpp by @mortbopet in #7571
• [FIRRTLUtils] Fix walkDrivers subfield id calculation by @uenoku in #7536
• [SV] Fix regop canonicalizer crashing. by @dtzSiFive in #7564
• [MooreToCore] Separate conversion pattern for moore.output by @maerhart in #7573
• [FIRRTL][GrandCentral] Fix crashes on error re:tryGetAs. by @dtzSiFive in #7576
• [FIRRTL][GrandCentral] Don't crash on missing keys, getAs. by @dtzSiFive in #7577
• [ESI] Manifest: change the schema to be more rational by @teqdruid in #7561
• [ESI][Runtime] Logging API by @teqdruid in #7569
• [MooreToCore] Support to lower unpacked struct type by @cepheus69 in #7565
• [Moore][NFC] Fix warning when building Moore components by @cepheus69 in #7566
• [ImportVerilog] Skip defparams which have been handled by slang. by @hailongSun2000 in #7582
• [HW] Fix crash when error encountered parsing hw.array. by @dtzSiFive in #7578
• [HW][HWTypes] Fix use of OptionalParseResult. by @dtzSiFive in #7575
• [FIRRTL][Folds] Fix mux fold if result type doesn't match operands. by @dtzSiFive in #7585
• [FIRRTL][Lexer] Don't crash on trailing slash in inline anno. by @dtzSiFive in #7579
• [FIRRTL][FIRParser] Defer inner symbols to post-processing, fix race. by @dtzSiFive in #7584
• [FIRRTL] Add back unambiguous path requirement. by @mikeurbach in #7588

Full Changelog: firtool-1.84.0...firtool-1.85.0

firtool-1.84.0

What's Changed

• [FIRRTL] Improve Layer Merge Performance by @seldridge in #7552
• [ESI] Make AcceleratorConnection::disconnect virtual by @mortbopet in #7554
• [FreezePaths] Add an optional argument, to get the operation name by @prithayan in #7549
• [ExportVerilog] Drop external module emission by @seldridge in #7558
• [firrtl] Add CheckLayers diagnostics pass by @youngar in #7547

Full Changelog: firtool-1.83.0...firtool-1.84.0

firtool-1.83.0

What's Changed

• [LLHD] Align signals with other wire/variable ops by @fabianschuiki in #7523
• [Moore] Improve WaitEventOp, lower to LLHD by @fabianschuiki in #7518
• [firrtl] Fix bug in sibling layer specialization by @seldridge in #7526
• [ExportVerilog] Avoid inlining unpacked array expressions to declarations for tool compatibility by @uenoku in #4548
• [LLHD] Let WaitOp observe plain values instead of signals by @maerhart in #7528
• [FIRRTL][FIRParser] Cache property constants. by @dtzSiFive in #7530
• [MooreToCore] Add always_comb and always_latch lowering support by @maerhart in #7532
• [ESI][Runtime] Generate C++ header files for constants by @teqdruid in #7517
• [CombFolds] Don't canonicalize extract(shl(1, x)) if shift is multiply used by @uenoku in #7527
• [MooreToCore] Ignore ConstantLike values in wait op by @fabianschuiki in #7540
• [FIRRTL][LowerLayers] Update rwprobe operations if possible. by @dtzSiFive in #7369
• [FIRRTL] Set output dirs on annotated blackboxes by @seldridge in #7541

Full Changelog: firtool-1.82.0...firtool-1.83.0

firtool-1.82.0

What's Changed

• [FIRRTL] Add list concatenation operation. by @mikeurbach in #7486
• [Verif] Generalize Formal Contracts by @dobios in #7495
• [FIRRTL] Add list concatenation parser support. by @mikeurbach in #7512
• [FIRRTL] Add list concatenation conversion to LowerClasses. by @mikeurbach in #7513
• Explain IR acronym in README by @parker-research in #7506
• [HW][CAPI] Add a function to get an empty InnerSymAttr by @SpriteOvO in #7504
• [PyCDE] Support for adding module constants to manifests by @teqdruid in #7510
• [Comb][Fold] Fix idemp n^2 and bugfix + more optimization. by @dtzSiFive in #7514
• [OM] Support list concatenation in the Evaluator. by @mikeurbach in #7511
• [LLHD] Relax sig parent constraint by @maerhart in #7515
• [Arc] Add Initial Cost Model by @elhewaty in #7360
• LowerLayers: fix how we emit layer bindfile headers by @rwy7 in #7516
• [FIRRTL] Add Inline Formal Test ops by @dobios in #7374
• [Arc] Add InitialOp and lowering support for FirReg preset values. by @fzi-hielscher in #7480
• [LowerIntmodules] Fix EICG_wrapper intrinsic lowering, swap en/test_en. by @dtzSiFive in #7519
• [firtool] Change layer specialization CLI interface by @youngar in #7520
• [FIRRTL] Add CheckRecursiveInstantiation diagnostic pass by @youngar in #7433
• [NFC] Add circt copy of upstream's linkify. by @dtzSiFive in #7521
• [FIRRTL] Update LowerClasses to alter what PathInfo stores. by @mikeurbach in #7522

New Contributors

• @parker-research made their first contribution in #7506

Full Changelog: firtool-1.81.1...firtool-1.82.0