firtool-1.81.1

What's Changed

• [Moore] Fix mem2reg implementation by @fabianschuiki in #7498
• [MooreToCore] More extract op lowerings by @maerhart in #7499
• [calyx] fix calyx canonicalization. by @linuxlonelyeagle in #7456
• [MooreToCore] Support AssignedVariableOp by @maerhart in #7500
• [MooreToCore] Support four-valued VariableOp without init by @fabianschuiki in #7502
• [MooreToCore] Support ConditionalOp by @fabianschuiki in #7501
• [MooreToCore] Support CaseZEq and CaseXZEq ops by @fabianschuiki in #7503
• [LLHD] Add llhd.delay operation by @maerhart in #7505
• [LLHD][NFC] Clean up regression tests a bit by @maerhart in #7507
• [LLHD] Remove RegOp by @maerhart in #7508
• [LLHD][NFC] Clean up some LLHD files by @maerhart in #7509
• [ESI][Manifest] Embed constants in manifest by @teqdruid in #7489
• [CreateSifiveMetadata] Update memory hierarchy paths to be pre-extrction by @prithayan in #7491
• [ESI][Runtime] Parse and expose manifest constants by @teqdruid in #7492
• [OM] Add list concatenation operation. by @mikeurbach in #7487

Full Changelog: firtool-1.81.0...firtool-1.81.1

firtool-1.81.0

What's Changed

• [ImportVerilog] Switch from SCF to CF dialect for control flow by @fabianschuiki in #7432
• [Docs][FIRRTL] Build and include docs for intrinsic ops by @SpriteOvO in #7444
• [CMake] Fix install failure with CMAKE_SLANG_FRONTEND_ENABLED enabled by @cepheus69 in #7437
• [Support] Allow erasing names in Namespace by @mortbopet in #7424
• [FIRRTL] Verify main module is a module, and is public. by @dtzSiFive in #7439
• [Ibis] Don't include design name in namespace in IbisContainersToHW by @mortbopet in #7425
• [FIRRTL] Verify RWProbeOp target has layer requirements. by @dtzSiFive in #7372
• [FIRRTL] Tweak printing of layers to avoid extra space. by @dtzSiFive in #7449
• Replaced 'replicate' to correctly named 'replace' flags by @jpien13 in #7442
• [Arc][Sim] Lower Sim DPI func to func.func and support dpi call in Arc by @uenoku in #7386
• [arcilator] Add an option to load shared lib into JIT engine by @uenoku in #7453
• [arcilator] Add JIT runtime environment library and stdio hooks by @fzi-hielscher in #7445
• [circt-lec] Accept two MLIR inputs by @uenoku in #7450
• [FIRRTL] Cache symbol table in LowerLayers by @seldridge in #7436
• [ExportVerilog] Add a lowering option to fix up empty modules by @uenoku in #7454
• [SimToSV] Add include guards to DPI import by @uenoku in #7459
• [ESI] Add option to build runtime as a static library by @mortbopet in #7455
• [ESI][Runtime] Poll method and optional service thread polling by @teqdruid in #7460
• [Moore] Add FVIntegerAttr by @fabianschuiki in #7461
• [Moore] Support four-valued integers in ConstantOp by @fabianschuiki in #7463
• [FIRRTL][Dedup] Reduce size of integer data hashed. by @dtzSiFive in #7469
• [FIRRTL][LowerLayers] Plumb support for errors. by @dtzSiFive in #7470
• [MooreToCore] Fix conversion and dyn_extract operation lowering by @maerhart in #7473
• [MooreToCore] Struct extract lowering support by @maerhart in #7475
• [FIRRTL][InferResets] Generalize FART to support sync reset by @jackkoenig in #7476
• [MooreToCore] Fix variable op lowering of aggregate types by @maerhart in #7481
• [MooreToCore] Support ProcedureOp and sequential assign operations by @maerhart in #7362
• [FIRRTL] Canonicalize multibit_mux with narrow index by @uenoku in #7373
• [FIRRTL] Fix sub-* op in layer block verifier by @seldridge in #7462
• [OM] Add AnyType C API and Python bindings. by @mikeurbach in #7488
• [OM] Add ListType C API and Python bindings. by @mikeurbach in #7490
• [HWArith] Make hwarith.icmp result an i1 by @teqdruid in #7413
• [Moore] Add more AssignedVariableOp canonicalizations by @fabianschuiki in #7477
• [Moore] Add constant materialization, fold constant conversions by @fabianschuiki in #7478
• bump llvm to tip of main by @mwachs5 in #7440
• [Moore] Power operator folders and canonicalizers by @maerhart in #7494
• [MooreToCore] Support StructExtractRefOp by @maerhart in #7497
• LLVM bump to include upstream verifier performance fix. by @dtzSiFive in #7496

New Contributors

• @jpien13 made their first contribution in #7442

Full Changelog: firtool-1.80.1...firtool-1.81.0

firtool-1.80.1

What's Changed

• [FIRRTL][Dedup] Improve diagnostic for failing to dedup due to public. by @dtzSiFive in #7426
• [Arc] Fix crash in the arc canonicalizer produced by the KeepOneVecOp optimization by @elhewaty in #7429
• [Arc] Make the canonicalizer shuffle the input vector elements before merging by @elhewaty in #7394
• [ImportVerilog] Add rvalue assignment pattern support by @fabianschuiki in #7428
• [OM] Add IntegerAttr -> Python int conversion by @seldridge in #7430
• [FIRRTL][LowerDPI] Lower FIRRTL vector to an open array type by @uenoku in #7305
• [Support] Add FVInt, a four-valued arbitrary precision integer by @fabianschuiki in #7422
• [Python][OM] Handle BoolAttr's before IntegerAttr's. by @dtzSiFive in #7438

Full Changelog: firtool-1.80.0...firtool-1.80.1

firtool-1.80.0

What's Changed

• [ESI Runtime] Port connect: add optional buffer size arg by @teqdruid in #7387
• [LLHD] Add TemporalCodeMotionPass by @maerhart in #7381
• [ImportVerilog] Support large integer constants by @fabianschuiki in #7391
• [ImportVerilog] Support for loop variables by @fabianschuiki in #7393
• [ImportVerilog] Support the power operator by @fabianschuiki in #7395
• [MooreToCore][NFC] Fix the visibility of hw.module. by @hailongSun2000 in #7396
• [FIRRTL] Touchup {parse,emit}-basic.fir for --parse-only. by @dtzSiFive in #7397
• [ESI Runtime] Distribute headers along with wheel by @teqdruid in #7400
• [Verif] Introduce Formal Contracts by @dobios in #7325
• [PrepareForEmission] Hoist registers in a procedural region with disallowLocalVariables by @uenoku in #7404
• [Moore] Clean up struct ops and add missing tests by @fabianschuiki in #7392
• [Scheduling] Replace macro use in problem definitions by @jopperm in #7320
• [FIRRTL] default layer specialization by @youngar in #7401
• [ImportVerilog] Support for String Types, String Literals by @wenhu1024 in #7403
• [ESI] MMIO: add read/write port to service by @teqdruid in #7407
• Support scf.if Op Lowering to Calyx by @jiahanxie353 in #6256
• [OM] Pass Python values back and forth, not Attributes. by @mikeurbach in #7417
• [docs] Remove confusing reset in Seq docs SV example by @TaoBi22 in #7419
• [FIRRTL][Dedup] Rework hashing for perf and bug fixes. by @dtzSiFive in #7420

New Contributors

• @wenhu1024 made their first contribution in #7403
• @jiahanxie353 made their first contribution in #6256

Full Changelog: firtool-1.79.0...firtool-1.80.0

firtool-1.79.0

What's Changed

• [ESI][Runtime] Publish Windows wheels by @teqdruid in #7363
• [firtool][test] Check layer specialization options work. by @dtzSiFive in #7364
• [SV][ExportVerilog] Add UnpackedOpenArrayType, cast op and emission by @uenoku in #7304
• [ImportVerilog] Add basic function support by @fabianschuiki in #7349
• [FIRRTL] Support layer-colored probes in force, force_initial. by @dtzSiFive in #7371
• [PrepareForEmission][Prettify] Extend allowExprInClock to handle new verif ops by @uenoku in #7332
• [FIRRTL] Add lowering support for inline layers by @rwy7 in #7322
• [CI] Report failure of clang-tidy by @rwy7 in #7355
• [ImportVerilog] Fix use after free by @fzi-hielscher in #7368
• [StringDebugInfoPred] Workaround FusedLoc bytecode issue by @uenoku in #7375
• [Seq] Fix ClockConstAttr definition to pass roundstrip test by @uenoku in #7379
• [ESI runtime] Host memory service by @teqdruid in #7367
• [CI][lit] Enable roundtrip tests in CI by @uenoku in #7377
• [ESI] Separate data delay from signaling standard by @teqdruid in #7354
• [Moore] Distinguish the dynamic and constant extract. by @hailongSun2000 in #7340
• [circt-bmc] Add LowerToBMC Pass by @TaoBi22 in #7343
• [FIRRTL][ProbesToSignals] Add pass to replace probes with signals. by @dtzSiFive in #7342

Full Changelog: firtool-1.78.1...firtool-1.79.0

What's Changed

• [ESI][Runtime] Publish Windows wheels by @teqdruid in #7363
• [firtool][test] Check layer specialization options work. by @dtzSiFive in #7364
• [SV][ExportVerilog] Add UnpackedOpenArrayType, cast op and emission by @uenoku in #7304
• [ImportVerilog] Add basic function support by @fabianschuiki in #7349
• [FIRRTL] Support layer-colored probes in force, force_initial. by @dtzSiFive in #7371
• [PrepareForEmission][Prettify] Extend allowExprInClock to handle new verif ops by @uenoku in #7332
• [FIRRTL] Add lowering support for inline layers by @rwy7 in #7322
• [CI] Report failure of clang-tidy by @rwy7 in #7355
• [ImportVerilog] Fix use after free by @fzi-hielscher in #7368
• [StringDebugInfoPred] Workaround FusedLoc bytecode issue by @uenoku in #7375
• [Seq] Fix ClockConstAttr definition to pass roundstrip test by @uenoku in #7379
• [ESI runtime] Host memory service by @teqdruid in #7367
• [CI][lit] Enable roundtrip tests in CI by @uenoku in #7377
• [ESI] Separate data delay from signaling standard by @teqdruid in #7354
• [Moore] Distinguish the dynamic and constant extract. by @hailongSun2000 in #7340
• [circt-bmc] Add LowerToBMC Pass by @TaoBi22 in #7343
• [FIRRTL][ProbesToSignals] Add pass to replace probes with signals. by @dtzSiFive in #7342

Full Changelog: firtool-1.78.1...firtool-1.79.0

firtool-1.78.1

What's Changed

• [ESI Runtime] If zlib not found, use FetchContent by @teqdruid in #7352
• [Seq] Canonicalize firreg with preset 0 by @prithayan in #7350
• [LLHD] Remove llhd-sim by @maerhart in #7351
• [LLHD] Use hw.inout instead of llhd.sig by @maerhart in #7353
• [LLHD] Replace entity with module by @maerhart in #6958
• [LLHD] Refactor llhd.proc and remove llhd.inst by @maerhart in #7357
• [Handshake] Fix library dependencies by @youngar in #7356
• [FIRRTL] LowerToHW: guard against folded operations by @youngar in #7358
• [firtool] Make layer specialization take a list of layers by @youngar in #7359

Full Changelog: firtool-1.78.0...firtool-1.78.1

firtool-1.78.0

What's Changed

• [CI] Drop macos-11 runners, use macos-12 in uploadReleaseArtifacts by @jackkoenig in #7319
• [llvm] Bump to 0870afaaaccde5b4bae37abfc982207ffafb8332 by @leonardt in #7318
• [MooreToCore] Lower var, read, and assign into LLHD. by @hailongSun2000 in #7297
• [circt-bmc] Add ExternaliseRegisters Pass by @TaoBi22 in #7285
• [Sim] Flatten format string concatenations in canonicalizer by @fzi-hielscher in #7316
• Reland "[FIRRTL][LowerClass] Pre-allocate namespaces before capturing refs (#7102)". by @mikeurbach in #7328
• [Sim] Add printing operations and transformation from non-procedural to procedural flavor by @fzi-hielscher in #7292
• [PyCDE] Simple transforms on channels by @teqdruid in #7330
• [PyCDE] Bundles: coerce method by @teqdruid in #7331
• [ExportVerilog] Add "context" to imported DPI functions by @uenoku in #7333
• [ImportVerilog] Fix unbased unsized literals of packed aggregate type by @fabianschuiki in #7336
• [Verif] Add formal test intent ops by @dobios in #7145
• [ImportVerilog]Dedup module Op by @mingzheTerapines in #7245
• [ImportVerilog] Accept empty packages by @fabianschuiki in #7334
• [ImportVerilog] [SROA] [Mem2Reg][Canonicalizers]Support Passes for Nested Type by @mingzheTerapines in #7158
• [ESI Runtime] Windows: python support and backend plugin loading by @teqdruid in #7338
• [SV] Add UnpackedArrayCreateOp by @uenoku in #7303
• [ImportVerilog] Handle $signed/$unsigned system tasks by @fabianschuiki in #7337
• [FIRRTL][FIRParser] Tokenize Commas by @mmaloney-sf in #7206
• [ImportVerilog] Allow enum variants in expressions by @fabianschuiki in #7339
• [MooreToCore] Support NegOp lowering by @maerhart in #7344
• [FIRRTL] AssignOutputDirs: Ensure absolute dirs end with trailing slash by @rwy7 in #7348

Full Changelog: firtool-1.77.0...firtool-1.78.0

Firtool Release 1.77.0

What's Changed

• [FIRRTL][NFC] Move IST -> FieldRef to FIRRTLUtils.h by @dtzSiFive in #7135
• [Docs][LTL] Add SVA Encodings to LTL rationale by @dobios in #7131
• [FIRRTL] Enable Wire Elimination by @darthscsi in #7073
• Capitalize Mode in github workflow. by @darthscsi in #7140
• [ExportVerilog][HW] Introduce HWEmittableModuleLike interface and use it for Prepare, NFC by @uenoku in #7004
• [FIRRTL][InferResets] Learn how to trace through nodes. by @dtzSiFive in #7141
• [Moore] Introduce RefType and tweak the related ops. by @hailongSun2000 in #7095
• [ExportVerilog] Support sv.func.* op emission by @uenoku in #7015
• [Docs] Update Python bindings pip instructions by @leonardt in #7147
• [Ibis] Divorce symbol and actual names in class and container ops by @mortbopet in #7123
• [FIRRTL] Support abstract reset in RWProbeOp by @dtzSiFive in #7136
• [FIRRTL] Cast to AnyRefType for metadata output port. by @mikeurbach in #7149
• [Handshake] Fix canonicalizer not going through rewriter for RAUW. by @dtzSiFive in #7052
• [MooreToCore] Add conversion support for module and instance. by @cepheus69 in #7132
• [FIRRTL] Emulate tap-as-passive for no-ref-ports option. by @dtzSiFive in #7109
• [FIRRTL][Parser] Never use forceable by @dtzSiFive in #7137
• [FIRRTL] Bump minimum to 2.0.0, remove partial connect by @seldridge in #5075
• [FIRRTL][Metadata] Add the path to the DUT, in the SiFive metadata class. by @prithayan in #7156
• [firtool] Remove LTLToCore pass from verification-flavor=immediate pipeline by @dobios in #7157
• [Moore] Introduce Mem2Reg to eliminate local variables by @hailongSun2000 in #7082
• [Moore] Add the SimplifyProcedures pass. by @hailongSun2000 in #7161
• [Sim] Add DPI func/call and lowering by @uenoku in #7042
• [ExportVerilog] Avoid using interface pass for PrepareForEmission, NFCI by @uenoku in #7168
• [FIRRTL] Add DPI call intrinsic and lowering pass by @uenoku in #7139
• [FIRRTL][ExportVerilog] Emit integers on DPI function as two state C-compatible types and clarify ABI by @uenoku in #7163
• [LowerDPI] Defer deletion of call ops to prevent inavlid access. by @fzi-hielscher in #7170
• [FIRRTL] Add a new op interface for combinational loop detection. by @prithayan in #7120
• [NFC][ExportVerilog] Rename generated options member. by @fzi-hielscher in #7172
• [Moore] Add evenOp to handle event controls. by @hailongSun2000 in #7154
• [ImportVerilog][MooreToCore]Lower moore.namedConstant to hw.constant & hw.wire by @mingzheTerapines in #7122
• Bump llvm by @uenoku in #7167
• [LowerDPI] Refactor the lowering logic to a helper struct, NFC by @uenoku in #7176
• [NFCI][Conversion] Refactor TableGen Pass includes by @fzi-hielscher in #7174
• [NFCI][Calyx] Refactor TableGen Pass includes by @fzi-hielscher in #7182
• [NFCI][Transforms] Refactor TableGen Pass includes by @fzi-hielscher in #7173
• [FIRRTL] Output directory control for layers and modules by @rwy7 in #6971
• [Verif] Add PrepareForFormal pass by @dobios in #7175
• [FIRRTL] Add pass to specialize layers by @youngar in #7160
• Fix paths in tests for windows builds by @rwy7 in #7185
• Add missing header includes by @rwy7 in #7187
• [NFCI][Comb][HW][Seq] Refactor TableGen Pass includes by @fzi-hielscher in #7180
• [NFCI][ESI][Ibis][MSFT] Refactor TableGen Pass includes by @fzi-hielscher in #7179
• [NFCI][LLHD][Moore][SV][Verif] Refactor TableGen Pass includes by @fzi-hielscher in #7183
• [FIRRTL][ExpandWhens] Add StmtExprVisitor to Visitor and Support DPI intrinsic in ExpandWhens by @uenoku in #7177
• [SimToSV] Fix DPICall lowering to use replaceOp by @uenoku in #7192
• [NFCI][FIRRTL] Refactor TableGen Pass includes by @fzi-hielscher in #7178
• [ExportVerilog] Fix two state type emission of aggregate types by @uenoku in #7189
• [FIRRTL][SpecializeLayers] Update doc with proper attribute name by @youngar in #7199
• [NFCI][DC][FSM][Handshake][Pipeline] Refactor TableGen Pass includes by @fzi-hielscher in #7181
• [NFCI][OM][SSP][SystemC] Refactor TableGen Pass includes by @fzi-hielscher in #7184
• [FIRRTL][SpecializeLayers] Fix incorrect CF leading to double free by @youngar in #7200
• [firtool] Move SpecializeLayers before LowerLayers by @youngar in #7201
• [FIRRTL][CheckCombLoops] Verify that detection works with region ops by @youngar in #7198
• [HW] Move the CombDataFlow op interface from FIRRTL to HW by @prithayan in #7195
• [FIRRTL][NFC] Fast-path removeAnnotations for operations having none. by @dtzSiFive in #7203
• [FIRRTL] AnnotationSet cleanups by @youngar in #7205
• [ESI][PyCDE] Callback service by @teqdruid in #7153
• [Moore] Support unconnected behavior by @cepheus69 in #7202
• [CI] Add a job to remove cache created by short integrations tests by @uenoku in #7214
• [Moore] Fix the stacking fault caused by cast and remove unused headers by @hailongSun2000 in #7219
• [FIRRTL] LHSType wrapper to indicate writable values. by @darthscsi in #7117
• [FIRRTL] SpecializeLayers: fix race condition by @youngar in #7218
• [HW] Clean up HWTypes, NFC by @uenoku in #7209
• README.md: remove link to dead build by @youngar in #7222
• [FIRRTL][Verif][LTL] Replace ltl.disable with an enable folded into verif.assert by @dobios in #7150
• [LowerClass] Run path tracking sequentially by @uenoku in #7221
• [ESI Runtime] Replace Cap'nProto with gRPC by @teqdruid in #7217
• [ESI Runtime] Read ports now invoke callbacks by @teqdruid in #7186
• [CI] Revert to working image and disable ESI runtime by @teqdruid in #7237
• [FIRRTL] Allow layers under when and match. by @dtzSiFive in #7234
• [ESI Runtime] Rename cmake targets, create full build one by @teqdruid in #7238
• Bump LLVM by @girishpai in #7223
• [FIRRTL] lower-layers.mlir: fix incorrect op name in test by @youngar in #7232
• [Moore] Add extra class declaration for RefType. by @hailongSun2000 in #7244
• [Interop] Use properties for inherent attributes. by @dtzSiFive in #7235
• [ImportVerilog] Support Generate constructs by @angelzzzzz in #7243
• [NFC][Seq] Remove unnecessary dependency of Seq on SV by @TaoBi22 in #7247
• [NFC][SV] Remove unnecessary dependency of SV on Verif by @TaoBi22 in #7249
• [Moore] Add LowerConcatRef pass to handle concat_ref. by @hailongSun2000 in #7216
• [ESI Runtime][NFC] Incorporate RPC server into ESICppRuntime by @teqdruid in #7241
• [ESI Runtime] Avoid using CIRCT_* cmake variables by @teqdruid in #7256
• [FIRRTL][ResolvePaths] Fix detection of agg target if alias. by @dtzSiFive in #7257
• [MooreToCore] Fix parse error for parameter by @mingzheTerapines in #7253
• [FIRRTL] Ensure hierpath considers owning module in LowerClasses. by @mikeurbach in #7272
• [Arc] Add VectorizeOp canonicalization by @elhewaty in #7146
• [Moore] To make SVModule having a graph region. by @hailongSun2000 in #7258
• [FIRRTL] Add input and output names to DPI intrinsic by @uenoku in #7265
• [ESI Runtime] Load backends as plugins by @teqdruid in #7260
• [PyCDE] R...

Release sifive/1/5/7

What's Changed

• Backport parentheses fix to 1.5.x by @uenoku in #7121

Full Changelog: sifive/1/5/6...sifive/1/5/7

Firtool Release 1.76.0

What's Changed

• [FIRRTL][NFC] Replace intmodules with intrinsic expressions in test. by @dtzSiFive in #7041
• [Arc] Add SplitFuncsPass by @TaoBi22 in #7027
• [Moore] Move IntType definition into ODS by @fabianschuiki in #7035
• [FIRRTL][Intrinsics] source materialization for inferred types. by @dtzSiFive in #7043
• [ESI][Cosim][NFC] Refactor cosim to divorce capnp from DPI by @teqdruid in #7045
• [SV] Add sv.func, sv.return and sv.func.call operations by @uenoku in #7003
• [SV] Add DPI import op by @uenoku in #7005
• [CreateSifiveMetadata] Fix a typo in the field name by @prithayan in #7046
• [SV][Folds] Fix ForOp canonicalizer to use rewriter. by @dtzSiFive in #7048
• [HW] Fix pattern returning success() without changing. by @dtzSiFive in #7053
• [Comb] Fix MuxRewriter to eraseOperand in rewriter-aware way. by @dtzSiFive in #7054
• [LLHD] Fix operand assignments not going through rewriter. by @dtzSiFive in #7055
• FileCheck directive fixup, now filecheck_lint-clean. by @dtzSiFive in #7057
• [Moore] Simplify and move RealType definition into ODS by @fabianschuiki in #7036
• [ESI][Runtime] Refactor cosim backend to be thread safe by @teqdruid in #7059
• [FIRRTL] Fix width of attribute in MuxPadSel canonicalizations. by @dtzSiFive in #7056
• [FIRRTL,PASS] Simple module summary looking for likely to dedup larger or numerous modules. This is to guide developers in using chisel better. by @darthscsi in #6935
• [FIRRTL][Import] Remove support for printf-encoded verif. by @dtzSiFive in #7030
• [FIRRTL][Folds] Fix patterns to use rewriter for RAUW by @dtzSiFive in #7049
• [LTL] Add repeat and until operators by @liuyic00 in #6989
• [FIRRTL] Reject intrinsic modules >= 4.0.0 by @dtzSiFive in #7009
• [PyCDE] Move build and publishing pipeline into repo by @teqdruid in #7062
• [FIRRTL][LowerClasses] Improve performance, NFC by @uenoku in #7060
• [FIRRTL] Convert Wires into Nodes by @darthscsi in #7067
• [FIRRTL] Register reset elimination based on invalid can look through nodes. by @darthscsi in #7069
• [FIRRTL] Remove unused and expensive API, NFC by @uenoku in #7076
• [FIRRTL] Preserve all analysis if nothing happens by @uenoku in #7077
• [FIRRTL] Limited invalid propagation. by @darthscsi in #7074
• LLVM bump by @youngar in #7079
• [ImportVerilog] Support member-access expression by @mingzheTerapines in #7039
• [ImportVerilog] Support set membership operator. by @angelzzzzz in #7066
• [LowerClasses] Ensure classes are instantiated by an object. by @prithayan in #7072
• [Verif] Add clocked Assert Assume Cover ops by @dobios in #7022
• [LTL] Add ops that allow for most of SVA to be modeled with LTL by @dobios in #7065
• [Seq] Fix incorrect folder by @uenoku in #7085
• [Arc] Modify VectorizeOp to support AnyType by @elhewaty in #7087
• [Moore] Move array types into ODS by @fabianschuiki in #7088
• [Moore] Support stripped type parsing and printing by @fabianschuiki in #7090
• [Moore] Move struct types into ODS by @fabianschuiki in #7091
• [Arc] Initial SLP support by @elhewaty in #7061
• [SMT] Added support for :pattern attribute by @luisacicolini in #6976
• [FIRRTL] Drop Hoistpassthroughs pass. by @dtzSiFive in #7097
• [CombToSMT] Register dependency on func by @maerhart in #7098
• [firtool] Add an option to export SV without SVA by @dobios in #7081
• [Arc] Fix crashes in FindInitialVectors Pass by @elhewaty in #7100
• [ImportVerilog][Moore] Support union type by @mingzheTerapines in #7084
• [FIRRTL][LowerClass] Pre-allocate namespaces before capturing references by @uenoku in #7102
• LLVM bump by @debs-sifive in #7103
• [ImportVerilog] Support parameter constants. by @angelzzzzz in #7083
• [FIRRTL] Visitor: Add missing ops, fix GenericIntrinsicOp visit. by @dtzSiFive in #7107
• [FIRRTL] Generate memportaccess op index as UInt. by @dtzSiFive in #7108
• CMake: Fix CIRCT_ENABLE_FRONTENDS to be string not bool. by @dtzSiFive in #7110
• [Arc] Add statistics to the FindInitialVectors pass by @elhewaty in #7113
• [NFC, FIRRTL] Rename StrictConnect to MatchingConnect. by @darthscsi in #7116
• [FIRRTL] Simplify path handling in ResolvePaths and LowerClasses. by @mikeurbach in #7129
• [FIRRTL] Actually copy the leading part of the path in LowerClasses. by @mikeurbach in #7130
• [Moore] Add module and instance port support by @fabianschuiki in #7112
• [FIRRTL][DropConst] Fix performance with many extmodule's. by @dtzSiFive in #7126
• [ImportVerilog] Add conditional operator. by @angelzzzzz in #6950

New Contributors

• @liuyic00 made their first contribution in #6989
• @mingzheTerapines made their first contribution in #7039
• @elhewaty made their first contribution in #7087

Full Changelog: firtool-1.75.0...firtool-1.76.0