firtool-1.87.0

What's Changed

• [FIRRTL] Make IMCP work with Layers by @seldridge in #7598
• [HW] Add reduction patterns to trim port list of top-level module by @maerhart in #7587
• [Arc] Fully support initialization through seq.initial by @uenoku in #7605
• [CMake] Consistently declare conversion libraries and simplify circt-opt link target list by @maerhart in #7610
• LLVM Bump by @maerhart in #7609
• [Moore] Add assert, assume, and cover ops. by @hailongSun2000 in #7589
• [FIRRTL] Allow local targets to be multiply-instantiated. by @mikeurbach in #7613
• [FIRRTL] Add InstanceInfo Analysis by @seldridge in #7612
• [LLHD][TCM] Simplify region directly by @maerhart in #7615
• [LLHD] Make process lowering best-effort and allow constants from outside the region by @maerhart in #7617
• [FIRRTL] Add features, cleanup InstanceInfo (again) by @seldridge in #7618
• Add verif.bmc VerifToSMT lowering by @TaoBi22 in #7603
• [SV] Add MacroRefOp to represet macro statement by @uenoku in #7607
• [MooreToCore] Alternative conditional lowering and type conversion fixes by @maerhart in #7625
• [circt-bmc] Add circt-bmc tool by @TaoBi22 in #7621
• [MooreToCore] Return early on non-convertable type by @maerhart in #7631
• [LLHD] Add DesequentializationPass by @maerhart in #7616
• [LLHD] Add Sig2Reg pass for graph regions by @maerhart in #7623
• [Moore] Drop named_constant op in favor of dbg.variable by @fabianschuiki in #7624
• [ImportVerilog] Add support for elaboration system tasks by @fabianschuiki in #7632
• [FIRRTL] Add verifier of single MarkDUTAnnotation by @seldridge in #7633
• [FIRRTL] Inliner: Support for ops with regions. by @dtzSiFive in #7398
• [firtool] Move LowerLayers later in pipeline. by @dtzSiFive in #7639
• [FIRRTL] Use walk, InstanceInfo in AddSeqMemPorts by @seldridge in #7599
• Bump LLVM to 556ec4a7261447d13703816cd3730a891441e52c. by @mikeurbach in #7641
• [ImportVerilog] Add support for $stop/$finish/$exit by @fabianschuiki in #7634
• [DC] Adding dc-print-dot pass by @luisacicolini in #7619
• [FIRRTL] Avoid InstanceGraphNode* in InstanceInfo by @seldridge in #7643
• [ImportVerilog] Add $display/$write/$info/$warning/$error/$fatal by @fabianschuiki in #7642
• [ImportVerilog] Add support for $clog2 by @fabianschuiki in #7645
• [FIRRTL] Error mixed DUT mems in AddSeqMemPorts by @seldridge in #7622
• [ImportVerilog] Support assignment patterns with integer type by @fabianschuiki in #7646
• [ImportVerilog] Insert missing conversions around instance ports by @fabianschuiki in #7647
• [FIRRTL][LowerLayers] Remove handling of some ref ops by @rwy7 in #7640
• [Analysis] Add OpCount Analysis by @TaoBi22 in #7644
• [Arc] Fix folding of initialized StateOp by @fzi-hielscher in #7653
• [Transforms][OpCountAnalysis] Add PrintOpCountPass by @TaoBi22 in #7654
• [MooreToCore] Lower moore.net to llhd.sig by @fabianschuiki in #7652
• [FIRRTL] Re-implement old EmitOMIR ports logic in LowerClasses. by @mikeurbach in #7651
• [Seq][Arc] Allow seq.initial to take immutable operands. Add a cast operation by @uenoku in #7656
• [FIRRTL] Add integer shift left property op by @maerhart in #7657
• [arcilator] Register Verif dialect by @owlxiao in #7655
• [OM] Add integer shift left op by @maerhart in #7658
• [FIRRTL] Add integer shift left parser support by @maerhart in #7659
• [FIRRTL] Add integer shift left conversion to LowerClasses by @maerhart in #7660

New Contributors

• @owlxiao made their first contribution in #7655

Full Changelog: firtool-1.86.0...firtool-1.87.0