Sifive 0.0.8 release

[FIRRTL] Preserve/Tap all "Named" Nodes or Wires (#2676)

Change end-to-end FIRRTL compilation behavior to preserve (via tapping) all
nodes and wires which are "named".  A "named" node or wire is one whose name
does not begin with an underscore.  Tapping is done by creating a "shadow node"
that is assigned the value of the actual wire and marked "don't touch".

This is done to enable better debug-ability of Chisel designs by enabling users
to always have references to named things they define in Chisel.  More
specifically, anytime a Chisel user defines a `val foo = <expression>`, CIRCT
will now produce a wire called "foo" in the output Verilog.

Add a parser option for controlling whether or not "named" wires and
nodes will be preserved from FIRRTL to Verilog.

Add a firtool command-line option for disabling name preservation during
FIRRTL parsing.

Signed-off-by: Schuyler Eldridge <[email protected]>