scripts: add a script to fix gigadevice firmwares libs

README.md

@@ -94,6 +94,8 @@ The conflicts at gd32 standard peripheral API are listed by the afected file(s).
 In general, a name is the conflict itself and that whould be reworked following
 the gd32 standard peripheral API rules.
 
+You can also check the refact tool at [scripts/lib_refactor](scripts/lib_refactor/)
+
  - `<firmware_library>_timer.h/c`: `timer_init()` should be prefixed with
  `gd32_` and become `gd32_timer_init()`.
  - `<firmware_library>_can.h/c`: all `CAN_` macros that collide with any

gd32e10x/cmsis/gd/gd32e10x/include/gd32e10x.h

@@ -4,10 +4,12 @@
 
  \version 2017-12-26, V1.0.1, firmware for GD32E10x
  \version 2020-09-30, V1.1.0, firmware for GD32E10x
+ \version 2020-12-31, V1.2.0, firmware for GD32E10x
+ \version 2022-06-30, V1.3.0, firmware for GD32E10x
 */
 
 /*
- Copyright (c) 2020, GigaDevice Semiconductor Inc.
+ Copyright (c) 2022, GigaDevice Semiconductor Inc.
 
  Redistribution and use in source and binary forms, with or without modification, 
 are permitted provided that the following conditions are met:
@@ -60,14 +62,6 @@ OF SUCH DAMAGE.
  #error "Please select the target board type used in your application (in gd32e10x.h file)"
  #endif
 #endif /* high speed crystal oscillator value */
-
-#if HXTAL_VALUE == 8000000
- #define HXTAL_VALUE_8M HXTAL_VALUE
-#elif HXTAL_VALUE == 25000000
- #define HXTAL_VALUE_25M HXTAL_VALUE
-#else
- #error "GD32E10X lib only support 8M and 25M oscillator (HXTAL)"
-#endif
 
 /* define startup timeout value of high speed crystal oscillator (HXTAL) */
 #if !defined (HXTAL_STARTUP_TIMEOUT)
@@ -201,9 +195,10 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
 #define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
 #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
 #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
-#ifndef BIT
+#ifndef BIT
 #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
-#endif
+#endif /* BIT */
+
 #define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) 
 #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
 

gd32e10x/cmsis/gd/gd32e10x/source/system_gd32e10x.c

@@ -61,6 +61,17 @@ OF SUCH DAMAGE.
 #define SEL_IRC8M 0x00U
 #define SEL_HXTAL 0x01U
 #define SEL_PLL 0x02U
+#define RCU_MODIFY(__delay) do{ \
+ volatile uint32_t i; \
+ if(0 != __delay){ \
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV2; \
+ for(i=0; i<__delay; i++){ \
+ } \
+ RCU_CFG0 |= RCU_AHB_CKSYS_DIV4; \
+ for(i=0; i<__delay; i++){ \
+ } \
+ } \
+ }while(0)
 
 /* set the system clock frequency and declare the system clock configuration function */
 #ifdef __SYSTEM_CLOCK_IRC8M
@@ -114,29 +125,26 @@ void SystemInit (void)
  /* reset the RCU clock configuration to the default reset state */
  /* Set IRC8MEN bit */
  RCU_CTL |= RCU_CTL_IRC8MEN;
-
- /* Reset CFG0 and CFG1 registers */
- RCU_CFG0 = 0x00000000U;
- RCU_CFG1 = 0x00000000U;
+ while(0U == (RCU_CTL & RCU_CTL_IRC8MSTB)){
+ }
+ RCU_MODIFY(0x50);
+ RCU_CFG0 &= ~RCU_CFG0_SCS;
 
  /* Reset HXTALEN, CKMEN, PLLEN, PLL1EN and PLL2EN bits */
  RCU_CTL &= ~(RCU_CTL_PLLEN |RCU_CTL_PLL1EN | RCU_CTL_PLL2EN | RCU_CTL_CKMEN | RCU_CTL_HXTALEN);
  /* disable all interrupts */
  RCU_INT = 0x00ff0000U;
 
+ /* Reset CFG0 and CFG1 registers */
+ RCU_CFG0 = 0x00000000U;
+ RCU_CFG1 = 0x00000000U;
+
  /* reset HXTALBPS bit */
  RCU_CTL &= ~(RCU_CTL_HXTALBPS);
 
  /* configure the system clock source, PLL Multiplier, AHB/APBx prescalers and Flash settings */
  system_clock_config();
-
- /*
- #ifdef VECT_TAB_SRAM
- nvic_vector_table_set(NVIC_VECTTAB_RAM,VECT_TAB_OFFSET);
- #else
- nvic_vector_table_set(NVIC_VECTTAB_FLASH,VECT_TAB_OFFSET);
- #endif
- */
+
 
 }
 

gd32e10x/standard_peripheral/include/gd32e10x_adc.h

@@ -5,10 +5,11 @@
  \version 2017-12-26, V1.0.0, firmware for GD32E10x
  \version 2020-09-30, V1.1.0, firmware for GD32E10x
  \version 2020-12-31, V1.2.0, firmware for GD32E10x
+ \version 2022-06-30, V1.3.0, firmware for GD32E10x
 */
 
 /*
- Copyright (c) 2020, GigaDevice Semiconductor Inc.
+ Copyright (c) 2022, GigaDevice Semiconductor Inc.
 
  Redistribution and use in source and binary forms, with or without modification, 
 are permitted provided that the following conditions are met:

gd32e10x/standard_peripheral/include/gd32e10x_bkp.h

@@ -5,10 +5,11 @@
  \version 2017-12-26, V1.0.0, firmware for GD32E10x
  \version 2020-09-30, V1.1.0, firmware for GD32E10x
  \version 2020-12-31, V1.2.0, firmware for GD32E10x
+ \version 2022-06-30, V1.3.0, firmware for GD32E10x
 */
 
 /*
- Copyright (c) 2020, GigaDevice Semiconductor Inc.
+ Copyright (c) 2022, GigaDevice Semiconductor Inc.
 
  Redistribution and use in source and binary forms, with or without modification, 
 are permitted provided that the following conditions are met:
@@ -179,7 +180,7 @@ typedef enum
 #define RTC_CLOCK_DIV_1 ((uint16_t)BKP_OCTL_CCOSEL) /*!< RTC clock div 1 */
 
 /* RTC clock calibration direction */
-#define RTC_CLOCK_SLOWED_DOWN ((uint16_t)0x0000U) /*!< RTC clock slow down */
+#define RTC_CLOCK_SLOW_DOWN  ((uint16_t)0x0000U) /*!< RTC clock slow down */
 #define RTC_CLOCK_SPEED_UP ((uint16_t)BKP_OCTL_CALDIR) /*!< RTC clock speed up */
 
 /* tamper pin active level */

gd32e10x/standard_peripheral/include/gd32e10x_crc.h

@@ -5,10 +5,11 @@
  \version 2017-12-26, V1.0.0, firmware for GD32E10x
  \version 2020-09-30, V1.1.0, firmware for GD32E10x
  \version 2020-12-31, V1.2.0, firmware for GD32E10x
+ \version 2022-06-30, V1.3.0, firmware for GD32E10x
 */
 
 /*
- Copyright (c) 2020, GigaDevice Semiconductor Inc.
+ Copyright (c) 2022, GigaDevice Semiconductor Inc.
 
  Redistribution and use in source and binary forms, with or without modification, 
 are permitted provided that the following conditions are met:

gd32e10x/standard_peripheral/include/gd32e10x_ctc.h

@@ -5,10 +5,11 @@
  \version 2017-12-26, V1.0.0, firmware for GD32E10x
  \version 2020-09-30, V1.1.0, firmware for GD32E10x
  \version 2020-12-31, V1.2.0, firmware for GD32E10x
+ \version 2022-06-30, V1.3.0, firmware for GD32E10x
 */
 
 /*
- Copyright (c) 2020, GigaDevice Semiconductor Inc.
+ Copyright (c) 2022, GigaDevice Semiconductor Inc.
 
  Redistribution and use in source and binary forms, with or without modification, 
 are permitted provided that the following conditions are met:
@@ -96,7 +97,6 @@ OF SUCH DAMAGE.
 #define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
 #define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
 #define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is selected */
-#define CTC_REFSOURCE_USBSOF CTL1_REFSEL(2) /*!< USBFS_SOF is selected */
 
 /* reference signal source prescaler definitions */
 #define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))

gd32e10x/standard_peripheral/include/gd32e10x_dac.h

@@ -5,10 +5,11 @@
  \version 2017-12-26, V1.0.0, firmware for GD32E10x
  \version 2020-09-30, V1.1.0, firmware for GD32E10x
  \version 2020-12-31, V1.2.0, firmware for GD32E10x
+ \version 2022-06-30, V1.3.0, firmware for GD32E10x
 */
 
 /*
- Copyright (c) 2020, GigaDevice Semiconductor Inc.
+ Copyright (c) 2022, GigaDevice Semiconductor Inc.
 
  Redistribution and use in source and binary forms, with or without modification, 
 are permitted provided that the following conditions are met:

gd32e10x/standard_peripheral/include/gd32e10x_dbg.h

@@ -5,10 +5,11 @@
  \version 2017-12-26, V1.0.0, firmware for GD32E10x
  \version 2020-09-30, V1.1.0, firmware for GD32E10x
  \version 2020-12-31, V1.2.0, firmware for GD32E10x
+ \version 2022-06-30, V1.3.0, firmware for GD32E10x
 */
 
 /*
- Copyright (c) 2020, GigaDevice Semiconductor Inc.
+ Copyright (c) 2022, GigaDevice Semiconductor Inc.
 
  Redistribution and use in source and binary forms, with or without modification, 
 are permitted provided that the following conditions are met:
@@ -55,7 +56,6 @@ OF SUCH DAMAGE.
 #define DBG_CTL_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
 #define DBG_CTL_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
 #define DBG_CTL_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */
-#define DBG_CTL_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */
 #define DBG_CTL_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
 #define DBG_CTL_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
 #define DBG_CTL_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */
@@ -103,13 +103,6 @@ typedef enum
  DBG_TIMER10_HOLD = BIT(30), /*!< hold TIMER10 counter when core is halted */
 }dbg_periph_enum;
 
-/* DBG_CTL0_TRACE_MODE configurations */
-#define CTL_TRACE_MODE(regval) (BITS(6,7) & ((uint32_t)(regval) << 6U))
-#define TRACE_MODE_ASYNC CTL_TRACE_MODE(0) /*!< trace pin used for async mode */
-#define TRACE_MODE_SYNC_DATASIZE_1 CTL_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */
-#define TRACE_MODE_SYNC_DATASIZE_2 CTL_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */
-#define TRACE_MODE_SYNC_DATASIZE_4 CTL_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */
-
 /* function declarations */
 /* read DBG_ID code register */
 uint32_t dbg_id_get(void);
@@ -128,7 +121,5 @@ void dbg_periph_disable(dbg_periph_enum dbg_periph);
 void dbg_trace_pin_enable(void);
 /* disable trace pin assignment */
 void dbg_trace_pin_disable(void);
-/* set trace pin mode */
-void dbg_trace_pin_mode_set(uint32_t trace_mode);
 
 #endif /* GD32E10X_DBG_H */

gd32e10x/standard_peripheral/include/gd32e10x_dma.h

@@ -5,10 +5,11 @@
  \version 2017-12-26, V1.0.0, firmware for GD32E10x
  \version 2020-09-30, V1.1.0, firmware for GD32E10x
  \version 2020-12-31, V1.2.0, firmware for GD32E10x
+ \version 2022-06-30, V1.3.0, firmware for GD32E10x
 */
 
 /*
- Copyright (c) 2020, GigaDevice Semiconductor Inc.
+ Copyright (c) 2022, GigaDevice Semiconductor Inc.
 
  Redistribution and use in source and binary forms, with or without modification, 
 are permitted provided that the following conditions are met:

gd32e10x/standard_peripheral/include/gd32e10x_exmc.h

@@ -5,10 +5,11 @@
  \version 2017-12-26, V1.0.0, firmware for GD32E10x
  \version 2020-09-30, V1.1.0, firmware for GD32E10x
  \version 2020-12-31, V1.2.0, firmware for GD32E10x
+ \version 2022-06-30, V1.3.0, firmware for GD32E10x
 */
 
 /*
- Copyright (c) 2020, GigaDevice Semiconductor Inc.
+ Copyright (c) 2022, GigaDevice Semiconductor Inc.
 
  Redistribution and use in source and binary forms, with or without modification, 
 are permitted provided that the following conditions are met:
@@ -163,21 +164,21 @@ typedef struct
 /* synchronous clock divide ratio */
 #define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
 #define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */
-#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */
-#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */
-#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */
-#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */
-#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */
-#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */
-#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */
-#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */
-#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */
-#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */
-#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */
-#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */
-#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK */
-#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */
-#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */
+#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< frequency EXMC_CLK = HCLK/2 */
+#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< frequency EXMC_CLK = HCLK/3 */
+#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< frequency EXMC_CLK = HCLK/4 */
+#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< frequency EXMC_CLK = HCLK/5 */
+#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< frequency EXMC_CLK = HCLK/6 */
+#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< frequency EXMC_CLK = HCLK/7 */
+#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< frequency EXMC_CLK = HCLK/8 */
+#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< frequency EXMC_CLK = HCLK/9 */
+#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< frequency EXMC_CLK = HCLK/10 */
+#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< frequency EXMC_CLK = HCLK/11 */
+#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< frequency EXMC_CLK = HCLK/12 */
+#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< frequency EXMC_CLK = HCLK/13 */
+#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< frequency EXMC_CLK = HCLK/14 */
+#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< frequency EXMC_CLK = HCLK/15 */
+#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< frequency EXMC_CLK = HCLK/16 */
 
 /* EXMC NOR/SRAM write mode */
 #define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */

gd32e10x/standard_peripheral/include/gd32e10x_exti.h

@@ -5,10 +5,11 @@
  \version 2017-12-26, V1.0.0, firmware for GD32E10x
  \version 2020-09-30, V1.1.0, firmware for GD32E10x
  \version 2020-12-31, V1.2.0, firmware for GD32E10x
+ \version 2022-06-30, V1.3.0, firmware for GD32E10x
 */
 
 /*
- Copyright (c) 2020, GigaDevice Semiconductor Inc.
+ Copyright (c) 2022, GigaDevice Semiconductor Inc.
 
  Redistribution and use in source and binary forms, with or without modification, 
 are permitted provided that the following conditions are met:

gd32e10x/standard_peripheral/include/gd32e10x_fmc.h

@@ -6,10 +6,11 @@
  \version 2020-05-11, V1.0.1, firmware for GD32E10x
  \version 2020-09-30, V1.1.0, firmware for GD32E10x
  \version 2020-12-31, V1.2.0, firmware for GD32E10x
+ \version 2022-06-30, V1.3.0, firmware for GD32E10x
 */
 
 /*
- Copyright (c) 2020, GigaDevice Semiconductor Inc.
+ Copyright (c) 2022, GigaDevice Semiconductor Inc.
 
  Redistribution and use in source and binary forms, with or without modification, 
 are permitted provided that the following conditions are met: