Counters

4 counters of different widths (8, 16, 32 and 64bits) and a parameterised counter implemented. Width of the parameterised counter edited with COUNTER_WIDTH. Counters count up to limit. If limit is zero, counters count indefinitely. When the limit reached, done becomes high and counting stops. Counters can be stoped with asserting en signal low. start signal works as synchronous reset. To start counting start should be kept high for at least 1 cycle.

Modules are simulated with Icarus Verilog.