Integrate Hyperbus peripheral

.gitignore

@@ -4,6 +4,7 @@ transcript
 .venv
 cheshire
 idma
+hyperbus
 
 # EMACS
 
@@ -30,6 +31,7 @@ utils/verible-verilog
 
 # SIM
 
+target/sim/models
 target/sim/vsim/work
 target/sim/vsim/transcript
 target/sim/vsim/trace*

.gitlab/gitlab-ci.yml

@@ -7,7 +7,7 @@
 # We initialize the nonfree repo, then spawn a sub-pipeline from it
 
 variables:
- VSIM_TESTS: '["testCluster", "testClusterOffload", "testMemBypass", "testPeripheralsGating"]'
+ VSIM_TESTS: '["testCluster", "testClusterOffload", "testMemBypass", "testPeripheralsGating", "testHyperbusAddr"]'
 
 stages:
  - nonfree

Bender.lock

@@ -164,6 +164,16 @@ packages:
  Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
  dependencies:
  - common_cells
+ hyperbus:
+ revision: f039e601c8b6590181734e6d26ff8b77aa380412
+ version: null
+ source:
+ Git: https://github.com/pulp-platform/hyperbus.git
+ dependencies:
+ - axi
+ - common_cells
+ - register_interface
+ - tech_cells_generic
  idma:
  revision: 9edf489f57389dce5e71252c79e337f527d3aded
  version: null

Bender.yml

@@ -17,6 +17,8 @@ dependencies:
  idma: { git: "https://github.com/pulp-platform/iDMA.git", rev: 9edf489f57389dce5e71252c79e337f527d3aded}
  memory_island: { git: "https://github.com/pulp-platform/memory_island.git", rev: 64828cb7a9ccc1f1656ec92d06129072f445c319 } # main branch
  apb: { git: "https://github.com/pulp-platform/apb.git", version: 0.2.4 }
+ hyperbus: { git: "https://github.com/pulp-platform/hyperbus.git", rev: f039e601c8b6590181734e6d26ff8b77aa380412 } # branch: chi/add_fsm_with_Tcsh
+ tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.12 }
 
 export_include_dirs:
  - hw/include
@@ -25,6 +27,7 @@ workspace:
  package_links:
  cheshire: cheshire
  idma: idma
+ hyperbus: hyperbus
 
 sources:
  - hw/chimera_pkg.sv
@@ -36,14 +39,16 @@ sources:
  - hw/chimera_cluster.sv
  - hw/chimera_clu_domain.sv
  - hw/chimera_memisland_domain.sv
+ - hw/hyperbus_wrap.sv
  - hw/chimera_top_wrapper.sv
 
  - target: any(simulation, test)
  files:
+ - target/sim/models/s27ks0641/s27ks0641.v
+ - target/sim/src/tb_chimera_pkg.sv
  - target/sim/src/vip_chimera_soc.sv
  - target/sim/src/fixture_chimera_soc.sv
  - target/sim/src/tb_chimera_soc.sv
- - target/sim/src/tb_chimera_pkg.sv
 
 vendor_package:
  - name: reggen

Makefile

@@ -14,6 +14,7 @@ VERIBLE_VERILOG_FORMAT ?= $(CHIM_UTILS_DIR)/verible-verilog/verible-verilog-form
 CHS_ROOT ?= $(shell $(BENDER) path cheshire)
 SNITCH_ROOT ?= $(shell $(BENDER) path snitch_cluster)
 IDMA_ROOT ?= $(shell $(BENDER) path idma)
+HYPERB_ROOT ?= $(shell $(BENDER) path hyperbus)
 
 CHS_XLEN ?= 32
 

bender.mk

@@ -8,4 +8,4 @@
 COMMON_TARGS ?=
 COMMON_TARGS += -t snitch_cluster -t cv32a6_convolve -t cva6 -t rtl
 
-SIM_TARGS = -t test -t sim
+SIM_TARGS = $(COMMON_TARGS) -t test -t sim

hw/chimera_pkg.sv

@@ -65,13 +65,14 @@ package chimera_pkg;
  localparam bit SnitchBootROM = 1;
  localparam bit TopLevelCfgRegs = 1;
  localparam bit ExtCfgRegs = 1;
+ localparam bit HyperCfgRegs = 1;
 
  // -------------------------------
  // | External Register Interface |
  // -------------------------------
 
  // SCHEREMO: Shared Snitch bootrom, one clock gate per cluster, External regs (PADs, FLLs etc...)
- localparam int ExtRegNum = SnitchBootROM + TopLevelCfgRegs + ExtCfgRegs;
+ localparam int ExtRegNum = SnitchBootROM + TopLevelCfgRegs + ExtCfgRegs + HyperCfgRegs;
  localparam int ClusterDataWidth = 64;
 
  localparam byte_bt SnitchBootROMIdx = 8'h0;
@@ -87,6 +88,11 @@ package chimera_pkg;
  localparam doub_bt ExtCfgRegsRegionStart = 64'h3000_2000;
  localparam doub_bt ExtCfgRegsRegionEnd = 64'h3000_5000;
 
+ // Hyperbus configuration registers: HyperBus
+ localparam byte_bt HyperCfgRegsIdx = 8'h3;
+ localparam doub_bt HyperCfgRegsRegionStart = 64'h3000_5000;
+ localparam doub_bt HyperCfgRegsRegionEnd = 64'h3000_6000;
+
  // --------------------------
  // | External AXI ports |
  // --------------------------
@@ -106,8 +112,8 @@ ExtClusters
 
  localparam aw_bt ClusterNarrowAxiMstIdWidth = 1;
 
- // Parameters for Memory Island
- localparam int MemIslandIdx = ClusterIdx[ExtClusters-1] + 1;
+ // Memory Island
+ localparam byte_bt MemIslandIdx = ClusterIdx[ExtClusters-1] + 1;
  localparam doub_bt MemIslRegionStart = 64'h4800_0000;
  localparam doub_bt MemIslRegionEnd = 64'h4804_0000;
 
@@ -118,13 +124,23 @@ ExtClusters
  localparam byte_bt MemIslNumWideBanks = 2;
  localparam shrt_bt MemIslWordsPerBank = 1024;
 
+ // Hyperbus
+ localparam byte_bt HyperbusIdx = MemIslandIdx + 1;
+ localparam doub_bt HyperbusRegionStart = 64'h5000_0000;
+ //TODO(smazzola): Correct size of HyperRAM?
+ localparam doub_bt HyperbusRegionEnd = HyperbusRegionStart + 64'h0800_0000;
+
+ localparam int unsigned LogDepth = 3;
+ localparam int unsigned SyncStages = 3;
+
  // -------------------
  // | Generate Cfg |
  // --------------------
 
  function automatic chimera_cfg_t gen_chimera_cfg();
  localparam int AddrWidth = DefaultCfg.AddrWidth;
  localparam int MemoryIsland = 1;
+ localparam int Hyperbus = 1;
 
  chimera_cfg_t chimera_cfg;
  cheshire_cfg_t cfg = DefaultCfg;
@@ -133,6 +149,7 @@ ExtClusters
 
  // Set all Chimera addresses as uncached
  cfg.Cva6ExtCieLength = 'h0;
+ cfg.Cva6ExtCieOnTop = 1;
 
  cfg.Vga = 0;
  cfg.SerialLink = 0;
@@ -150,21 +167,26 @@ ExtClusters
 
  // SCHEREMO: Two ports for each cluster: one to convert stray wides, one for the original narrow
  cfg.AxiExtNumMst = ExtClusters + $countones(ChimeraClusterCfg.hasWideMasterPort);
- cfg.AxiExtNumSlv = ExtClusters + MemoryIsland;
- cfg.AxiExtNumRules = ExtClusters + MemoryIsland;
+ cfg.AxiExtNumSlv = ExtClusters + MemoryIsland + Hyperbus;
+ cfg.AxiExtNumRules = ExtClusters + MemoryIsland + Hyperbus;
 
- cfg.AxiExtRegionIdx = {MemIslandIdx, ClusterIdx};
- cfg.AxiExtRegionStart = {MemIslRegionStart, ClusterRegionStart};
- cfg.AxiExtRegionEnd = {MemIslRegionEnd, ClusterRegionEnd};
+ cfg.AxiExtRegionIdx = {HyperbusIdx, MemIslandIdx, ClusterIdx};
+ cfg.AxiExtRegionStart = {HyperbusRegionStart, MemIslRegionStart, ClusterRegionStart};
+ cfg.AxiExtRegionEnd = {HyperbusRegionEnd, MemIslRegionEnd, ClusterRegionEnd};
 
  // REG CFG
  cfg.RegExtNumSlv = ExtRegNum;
  cfg.RegExtNumRules = ExtRegNum;
- cfg.RegExtRegionIdx = {ExtCfgRegsIdx, TopLevelCfgRegsIdx, SnitchBootROMIdx};
+ cfg.RegExtRegionIdx = {HyperCfgRegsIdx, ExtCfgRegsIdx, TopLevelCfgRegsIdx, SnitchBootROMIdx};
  cfg.RegExtRegionStart = {
- ExtCfgRegsRegionStart, TopLevelCfgRegsRegionStart, SnitchBootROMRegionStart
+ HyperCfgRegsRegionStart,
+ ExtCfgRegsRegionStart,
+ TopLevelCfgRegsRegionStart,
+ SnitchBootROMRegionStart
+ };
+ cfg.RegExtRegionEnd = {
+ HyperCfgRegsRegionEnd, ExtCfgRegsRegionEnd, TopLevelCfgRegsRegionEnd, SnitchBootROMRegionEnd
  };
- cfg.RegExtRegionEnd = {ExtCfgRegsRegionEnd, TopLevelCfgRegsRegionEnd, SnitchBootROMRegionEnd};
 
  // ACCEL HART/IRQ CFG
  cfg.NumExtIrqHarts = ExtCores;