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This PR:
integrates the Hyperbus peripheral in the Chimera top RTL
integrates the HyperRAM VIP in the Chimera testbench
adds an addressability test for the Hyperbus and adds it to the CI
Config registers are still to be added add config registers to hyperbus #43
What address range should we use for the HyperRAM? https://github.com/pulp-platform/chimera/blob/smazzola/hyperbus/hw/chimera_pkg.sv#L128-L130