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Pull request for fix of SDA glitch #5

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Commits on Nov 27, 2022

  1. Prepare Verilog RTL For Fix

        1. Add default clause to FSMs in Bit
           Controller and Byte Controller
        2. Eliminate (for now) slave_reset from the
           second master FSM reset clause
    bobnewgard committed Nov 27, 2022
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Commits on Dec 28, 2022

  1. Implement Fix for SDA Glitch

        1. Eliminate unused reg slave_adr_received_d
           in the bit controller since it depresses
           the coverage score
        2. Whitespace changes in states ST_SL_WAIT,
           ST_SL_WR, and ST_SL_RD
        3. Add reset to ST_IDLE upon slave_reset in
           state ST_SL_WR
    bobnewgard committed Dec 28, 2022
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Commits on Jan 1, 2023

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