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This pull request is associated with issue #4.
The changes in this pull request have been verified only in the testbench at https://codeberg.org/bobn/tb_i2c_herveille_oc. No hardware validation has been done.
The important change is to the
ST_SL_WR
state of the byte controllerc_state
FSM. Instead of resetting everything uponslave_reset
, the change transitions the FSM toST_IDLE
when the FSM is inST_SL_WR
and slave_reset is high.I think that the addition of default clauses in FSM case statements is important in the presence of a single event upset (SEU). Of course, SEU mitigation only applies when targeting RAM-based FPGAs.
The FSM without a default clause would go into an indeterminate state, perhaps detectably, but perhaps not. With the default clause, the FSM halts, which is always detectable.
All whitespace changes are immaterial.