feat: VPL simulation files fix: lab 2 drills feat: first two courses latex slides feat: add the opensource toolchain Dockerfile #29
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chapters/intro/soc/reading/README.md#L8
WARNING:REPEATED_WORD: Possible repeated word: 'to'
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chapters/verilog/basic/drills/README.md#L4
WARNING:TYPO_SPELLING: 'modul' may be misspelled - perhaps 'module'?
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chapters/verilog/basic/drills/README.md#L12
ERROR:TRAILING_WHITESPACE: trailing whitespace
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chapters/verilog/basic/drills/tasks/adder_4bits/adder_4bits.v#L15
ERROR:TRAILING_WHITESPACE: trailing whitespace
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chapters/verilog/basic/drills/tasks/adder_6bits/adder_6bits.v#L7
ERROR:TRAILING_WHITESPACE: trailing whitespace
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ERROR:MISSING_SIGN_OFF: Missing Signed-off-by: line(s)
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WARNING:COMMIT_MESSAGE: Missing commit description - Add an appropriate one
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