feat: VPL simulation files fix: lab 2 drills feat: first two courses latex slides feat: add the opensource toolchain Dockerfile

.devcontainer/open.Dockerfile

@@ -0,0 +1,27 @@
+# syntax=docker/dockerfile:1
+FROM ubuntu:22.04
+
+LABEL maintainer="[email protected]"
+LABEL version="0.1"
+LABEL description="The open source toolchain docker image for the Computer Architecture course"
+
+# for apt-get
+# https://serverfault.com/questions/949991/how-to-install-tzdata-on-a-ubuntu-docker-image
+ARG DEBIAN_FRONTEND=noninteractive
+ENV TZ=Europe/Bucharest
+
+RUN apt-get update && \
+ apt-get upgrade -y && \
+ apt-get install -y nano git unzip wget gedit make gcc g++
+# install gtkwave through apt-get
+# https://github.com/gtkwave/gtkwave
+RUN apt-get install -y gtkwave
+
+# install icaurs
+# https://github.com/steveicarus/iverilog
+RUN apt-get install -y iverilog
+
+# install yosys
+RUN apt-get install -y yosys
+# install verilator
+RUN apt-get install -y verilator

chapters/guides/docker/macos/README.md

@@ -0,0 +1,56 @@
+# Utilizare imagine docker MacOS
+
+## Cerințe necesare
+
+### Docker Desktop
+
+Instalare [Docker Desktop](https://www.docker.com/products/docker-desktop/).
+
+### Instalre XQuartz
+
+Instalare [XQuartz](https://www.xquartz.org/)
+
+### Visual Studio Code
+
+Descărcați și instalați [Visual Studio Code](https://code.visualstudio.com/download)
+
+### Clonați repo-ul materiei
+
+```bash
+git clone https://github.com/cs-pub-ro/computer-architecture.git
+```
+
+## Rulare
+
+### Porniți XQuartz
+
+1. Deschideți Applications > Utilities > XQuartz
+
+
+### Opțiunea 1 din Visual Studio Code
+
+1. Deschideți directorul repo-ului în Visual Studio Code.
+```bash
+code computer-architecture
+```
+
+2. Instalați extensia [Dev Containers](https://marketplace.visualstudio.com/items?itemName=ms-vscode-remote.remote-containers).
+
+3. După veți avea opțiunea "Dev Containers: Reopen in container" (`CTRL+SHIFT+P`).
+
+### Opțiunea 2 prin docker
+
+1. Descărcați imaginea cu docker
+```bash
+docker pull gitlab.cs.pub.ro:5050/ac/ac-public/vivado-slim:1.0.0
+```
+
+2. Rulați un container cu imaginea
+```bash
+docker run --rm -it -v /dev:/dev gitlab.cs.pub.ro:5050/ac/ac-public/vivado-slim:1.0.0 /bin/bash
+```
+
+3. Rulați vivado din imagine
+```bash
+vivado
+```

chapters/guides/docker/windows/README.md

@@ -114,3 +114,9 @@ docker run --rm -it -v /dev:/dev gitlab.cs.pub.ro:5050/ac/ac-public/vivado-slim:
 ```bash
 vivado
 ```
+
+
+## Troubleshooting
+### Vivado nu vede seriala catre FPGA (laptop)
+
+Urmăriți tutorialul până la finalul sesiunii "Attach the device to wsl2" [usbipd](https://hackmd.io/@aeefs2Y8TMms-cjTDX4cfw/r1fqAa_Da)

chapters/verilog/basic/assigments/mux/.gitignore

@@ -0,0 +1,2 @@
+*.vvp
+*.vcd

chapters/verilog/basic/assigments/mux/Makefile

@@ -0,0 +1,47 @@
+COMPILER=iverilog
+INTERPRETER=vvp
+SIMULATOR=gtkwave
+FLAGS=-Wall -Winfloop
+SOLUTION_FLAGS=-DSEL_WIDTH=2
+TOP_MODULE=mux
+TOP_SIM_MODULE=test_${TOP_MODULE}
+TOP_EVALUATE_MODULE=evaluate_${TOP_MODULE}
+SOLUTION_MODULE=solution_${TOP_MODULE}
+SOLUTION_SIM_MODULE=test_${SOLUTION_MODULE}
+OTHER_SOURCES=
+DUMP_VCD_FILE=test.vcd
+EVALUATE_FILE=evaluate.out
+GRADE_SCRIPT=grade.sh
+
+all: build
+
+build:
+ $(COMPILER) $(FLAGS) $(TOP_MODULE).v $(TOP_SIM_MODULE).v $(OTHER_SOURCES) -o $(TOP_MODULE).vvp
+
+build_solution:
+ $(COMPILER) $(FLAGS) ${SOLUTION_FLAGS} ${SOLUTION_SIM_MODULE}.v ${SOLUTION_MODULE}.v $(OTHER_SOURCES) -o $(SOLUTION_MODULE).vvp
+
+build_evaluate:
+ $(COMPILER) $(FLAGS) ${SOLUTION_FLAGS} ${TOP_MODULE}.v ${SOLUTION_MODULE}.v ${TOP_EVALUATE_MODULE}.v $(OTHER_SOURCES) -o $(TOP_EVALUATE_MODULE).vvp
+
+
+run: build
+ $(INTERPRETER) $(TOP_MODULE).vvp
+
+run_solution: build_solution
+ $(INTERPRETER) $(SOLUTION_MODULE).vvp
+
+run_evaluate: build_evaluate
+ $(INTERPRETER) $(TOP_EVALUATE_MODULE).vvp &> $(EVALUATE_FILE)
+
+simulate: run
+ $(SIMULATOR) $(DUMP_VCD_FILE)
+
+simulate_solution: run_solution
+ $(SIMULATOR) $(DUMP_VCD_FILE)
+
+evaluate: run_evaluate
+ ./${GRADE_SCRIPT} $(EVALUATE_FILE)
+
+clean:
+ rm *.vvp $(DUMP_VCD_FILE) $(EVALUATE_FILE)

chapters/verilog/basic/assigments/mux/README.md

@@ -0,0 +1 @@
+Implementați un multiplexor. Apăsați butonul run din VPL pentru a afla tipul multiplexorului pe care trebuie sa îl implementați.

chapters/verilog/basic/assigments/mux/evaluate_mux.v

@@ -0,0 +1,46 @@
+`timescale 1ns / 1ps
+module evaluate_mux;
+ localparam l_p_sel_width = `SEL_WIDTH;
+ //Inputs
+ reg [(l_p_sel_width-1):0] l_r_sel;
+ reg [(2**l_p_sel_width)-1:0] l_r_in;
+
+ //Outputs
+ wire l_w_out;
+ wire l_w_sout;
+
+ //local variables for loop
+ integer i,j;
+
+ //Module initialization
+ mux uut (
+ .o_w_out(l_w_out),
+ .i_w_in(l_r_in),
+ .i_w_sel(l_r_sel)
+ );
+
+ solution_mux suut (
+ .o_w_out(l_w_sout),
+ .i_w_in(l_r_in),
+ .i_w_sel(l_r_sel)
+ );
+
+ //Simulation tests
+ initial begin
+ for (i = 0; i < (2**l_p_sel_width); i = i + 1) begin
+ l_r_in = 1 << i;
+ for (j = 0; j < (2**l_p_sel_width); j = j + 1) begin
+ l_r_sel = j;
+ #5;
+ if (l_w_out !== l_w_sout) begin
+ $display("Error: (hex_values) l_w_out = %0h correct %0h, sel: %0h in = %0h", l_w_out, l_w_sout, j, l_r_in);
+ end else begin
+ $display("OK");
+ end
+ #5;
+ end
+ end
+ //finish the simulation
+ $finish;
+ end
+endmodule

chapters/verilog/basic/assigments/mux/grade.sh

@@ -0,0 +1,21 @@
+#!/bin/bash
+if [[ $# -ne 1 ]]; then
+ echo 'Too many/few arguments, expecting one' >&2
+ exit 1
+fi
+
+EVALUATE_FILE=$1
+#--- remove multiple spaces --- 
+cat $EVALUATE_FILE | sed 's/ */ /g' > dummy.out
+mv dummy.out $EVALUATE_FILE
+
+#--- remove blank lines ---
+cat $EVALUATE_FILE | sed '/^\s*$/d' > dummy.out
+mv dummy.out $EVALUATE_FILE
+
+# Calculate number of correct test versus wrong test
+correct_test_no=$(awk '$1=="OK" { print $0 }' $EVALUATE_FILE | wc -l | awk '{ print $1 }')
+test_no=$(wc -l $EVALUATE_FILE| awk '{ print $1 }')
+grade=$( expr $correct_test_no \* 100 / $test_no)
+
+echo $grade

chapters/verilog/basic/assigments/mux/mux.v

@@ -0,0 +1,5 @@
+module mux(
+// TODO: add inputs o_w_out,i_w_in,i_w_sel
+);
+// TODO: implement mux x:1
+endmodule

chapters/verilog/basic/assigments/mux/solution_mux.v

@@ -0,0 +1,7 @@
+module solution_mux (
+ output wire o_w_out,
+ input wire [((2**`SEL_WIDTH)-1):0] i_w_in,
+ input wire [`SEL_WIDTH-1:0] i_w_sel
+);
+ assign o_w_out = i_w_in[i_w_sel];
+endmodule

chapters/verilog/basic/assigments/mux/test_mux.v

@@ -0,0 +1,17 @@
+`timescale 1ns / 1ps
+module test_mux;
+ //Inputs
+
+ //Outputs
+
+ //local variables for loop
+ integer i,j;
+
+ //Module initialization
+
+ //Simulation tests
+ initial begin
+ //finish the simulation
+ $finish;
+ end
+endmodule

chapters/verilog/basic/assigments/mux/test_solution_mux.v

@@ -0,0 +1,49 @@
+`timescale 1ns / 1ps
+module test_mux;
+ localparam l_p_sel_width = `SEL_WIDTH;
+ //Inputs
+ reg [(l_p_sel_width-1):0] l_r_sel;
+ reg [(2**l_p_sel_width)-1:0] l_r_in;
+
+ //Outputs
+ wire l_w_out;
+
+ //local variables for loop
+ integer i,j;
+
+ //Module initialization
+ solution_mux uut (
+ .o_w_out(l_w_out),
+ .i_w_in(l_r_in),
+ .i_w_sel(l_r_sel)
+ );
+
+ //Simulation tests
+ initial begin
+ //wave files
+ $dumpfile("test.vcd");
+ // dumpp all variables
+ $dumpvars;
+ // monitor varibles changes in values
+ $monitor(
+ "Time = %0t, ", $time,
+ "l_w_out = %0h, ", l_w_out,
+ "l_r_sel = %0h, ", l_r_sel,
+ "l_r_in = %0h", l_r_in
+ );
+
+ for (i = 0; i < (2**l_p_sel_width); i = i + 1) begin
+ l_r_in = 1 << i;
+ for (j = 0; j < (2**l_p_sel_width); j = j + 1) begin
+ l_r_sel = j;
+ #5;
+ if (l_w_out !== l_r_in[j]) begin
+ $display("Error: l_w_out = %0h, l_r_in[%0d] = %0h", l_w_out, j, l_r_in[j]);
+ end
+ #5;
+ end
+ end
+ //finish the simulation
+ $finish;
+ end
+endmodule

chapters/verilog/basic/assigments/mux/vpl_evaluate.sh

@@ -0,0 +1,61 @@
+#!/bin/bash
+#
+# vpl_evaluate.sh script 
+
+source common_script.sh
+
+#./vpl_run.sh
+TOP_MODULE=mux
+TOP_SIM_MODULE=test_${TOP_MODULE}
+TOP_EVALUATE_MODULE=evaluate_${TOP_MODULE}
+SOLUTION_MODULE=solution_${TOP_MODULE}
+OTHER_SOURCES=
+maxGrade=100
+
+# get the variation
+variation=\$(date +"%d%H")
+if [ \$((variation % 2)) == 0 ]; then
+ variation=variation
+else
+ variation=\$(expr \$variation - 1)
+fi
+
+start_sel_no_bits=2
+end_sel_no_bits=4
+sel_no_bits=\$(awk -v seed="\$variation" -v start_number="\$start_sel_no_bits" -v end_number="\$end_sel_no_bits" 'BEGIN {
+ # seed
+ srand(seed)
+ print start_number + int((end_number - start_number) * rand())
+}')
+
+
+# BUILD the code
+iverilog ${TOP_MODULE}.v ${SOLUTION_MODULE}.v ${TOP_EVALUATE_MODULE}.v ${OTHER_SOURCES} -P p_sel_width=${sel_no_bits} -o ${TOP_MODULE}.vvp
+# RUN the code
+vvp ${TOP_MODULE}.vvp &> user.out
+
+
+#--- remove multiple spaces --- 
+cat user.out | sed 's/ */ /g' > dummy.out
+mv dummy.out user.out
+
+#--- remove blank lines ---
+cat user.out | sed '/^\s*$/d' > dummy.out
+mv dummy.out user.out
+
+# Calculate number of correct test versus wrong test
+correct_test_no=$(awk '$1=="OK" { print $0 }' user.out | wc -l | awk '{ print $1 }')
+test_no=$(wc -l user.out | awk '{ print $1 }')
+grade=$( expr $correct_test_no \* 100 / $test_no)
+
+echo "#!/bin/bash" > vpl_execution
+
+# if not max grade print the first error line
+if (( $grade < $maxGrade )) ; then
+text=$(awk '$1!="OK" { print $0 }' user.out | awk 'NR==1 { print $0 }')
+echo "echo '$text' " >> vpl_execution
+fi
+
+echo "echo 'Grade :=>> $grade' " >> vpl_execution
+
+chmod +x vpl_execution