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Add Lakeroad egglog backend #4
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Commits on Sep 3, 2023
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Commits on Sep 4, 2023
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Commits on Sep 5, 2023
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ast: Substitute rvalues when parsing out print arguments
Apply the local substitutions stemming from process context when parsing out format arguments to `$display` or other statements.
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Commits on Sep 6, 2023
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sv: support assignments within expressions
- Add support for assignments within expressions, e.g., `x[y++] = z;` or `x = (y *= 2) - 1;`. The logic is handled entirely within the parser by injecting statements into the current procedural block. - Add support for pre-increment/decrement statements, which are behaviorally equivalent to post-increment/decrement statements. - Fix non-standard attribute position used for post-increment/decrement statements.
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xprop: Fix polarity errors and generate hdlnames
* Fixes a non-deterministic polarity error for $eqx/$nex cells * Fixes a deterministic polarity error for $_NOR_ and $_ORNOT_ cells * Generates hdlnames when xprop is run after flatten
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Commits on Sep 7, 2023
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Commits on Sep 8, 2023
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renamed passname to booth, replaced connect_sigSpecToWire with connec…
…t, updated test script
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Commits on Sep 10, 2023
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Commits on Sep 11, 2023
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Merge pull request YosysHQ#3915 from povik/sim-print
sim: Add print support
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Merge pull request YosysHQ#3918 from povik/print-sampling-fix
ast: Substitute rvalues when parsing out print arguments
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Commits on Sep 12, 2023
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Merge pull request YosysHQ#3926 from YosysHQ/update_abc2
Update ABC to latest
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Merge pull request YosysHQ#3927 from YosysHQ/verific_memory
verific - respect order of read and write for rams
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Merge pull request YosysHQ#3892 from QuantamHD/dont_use
abc: Exposes dont_use flag in ABC
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mem: Fix index confusion in write port merging
Fix mistaking the read-port and write-port indices for each other when we are adding the partial transparency emulation to be able to merge two write ports.
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fmt: Fix C++ string assertion when buf is empty
Signed-off-by: gatecat <[email protected]>
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Merge pull request YosysHQ#3928 from povik/mem-wr-merge-transpemu-fix
mem: Fix index confusion in write port merging
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Merge pull request YosysHQ#3929 from YosysHQ/gatecat/fmt-fix
fmt: Fix C++ string assertion when buf is empty
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Commits on Sep 13, 2023
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Initial dft_tag implementation
This is still missing a mode to rewrite $overwrite_tag and $original_tag by injecting $set_tag and $get_tag in the right places. It's also missing bit-precise propagation models for shifts and arithmetic and requires the design to be flattened.
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dft_tag: Implement
$overwrite_tag
and$original_tag
This does not correctly handle an `$overwrite_tag` on a module output, but since we currently require the user to flatten the design for cross-module dft, this cannot be observed from within the design, only by manually inspecting the signals in the design.
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Merge pull request YosysHQ#3903 from jix/dft-future_ff
Basic support for tag primitives and `$future_ff`
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Merge pull request YosysHQ#3931 from whitequark/update-abc
Update ABC for WASI support
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Commits on Sep 14, 2023
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Commits on Sep 15, 2023
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Alphabetize headers to be installed, include some missing required on…
…es for plugins, fixes chipsalliance/synlig#1972 dau-dev/tools#6
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Commits on Sep 18, 2023
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Merge pull request YosysHQ#3924 from andyfox-rushc/master
multpass -- create Booth Encoded multipliers for
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Commits on Sep 19, 2023
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Merge pull request YosysHQ#3943 from YosysHQ/verific_lineinfo
Set src attribute for verific with full info
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Commits on Sep 20, 2023
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Merge pull request YosysHQ#3920 from zachjs/asgn-expr
sv: support assignments within expressions
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Merge pull request YosysHQ#3930 from povik/verific-test-memsemantics
verific: Add test of accurate semantics in memory inference
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Speed up TopoSort. The main sorting algorithm implementation in TopoS…
…ort::sort_worker is 11-12x faster. Overall, the complete sequence of building the graph and sorting is about 2.5-3x faster. The overall impact in e.g. the replace_const_cells optimization pass is a ~25% speedup. End-to-end impact on our synthesis flow is about 3%.
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Commits on Sep 21, 2023
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This PR speeds up by roughly 17% across a wide spectrum of designs tested at Google. Particularly for the mux generation pass. Co-authored-by: Rasmus Larsen <[email protected]> Signed-off-by: Ethan Mahintorabi <[email protected]>
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Speed up the autoname pass by 3x. (YosysHQ#3945)
* Speed up the autoname pass by 2x. This is accomplished by only constructing IdString objects for plain strings that have a higher score. * Defer creating IdStrings even further. This increases the speedup to 3x.
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Commits on Sep 22, 2023
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Commits on Sep 25, 2023
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booth: Move away from explicit
Wire
pointersTo represent intermediate signals use the `SigBit`/`SigSpec` classes as is customary in the Yosys codebase. Do not pass around `Wire` pointers unless we have special reason to.
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booth: Streamline the low-level circuit emission
For the basic single-bit operations, opt for gate cells (`$_AND_` etc.) instead of the coarse cells (`$and` etc.). For the emission of cells move to the conventional module methods (`module->addAndGate`) away from the local helpers. While at it, touch on the surrounding code.
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booth: Make more use of appropriate helpers
Use the `addFa` helper, do not misuse `new_id` and make other changes to the transformation code.
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Commits on Sep 26, 2023
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ast/simplify: Make tweaks in advance of big in_lvalue/in_param change
The following commit will replace the way in_lvalue/in_param is being tracked in the simplify code. Make tweaks in advance so that it will be easier to make the old way and the new way agree. These changes all should be innocuous.
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ast/simplify: Make in_lvalue/in_param into props of AST nodes
Instead of passing around in_lvalue/in_param flags to simplify, we make the flags into properties of the AST nodes themselves. After the tree is first parsed, we once do ast->fixup_hierarchy_flags(true) to walk the full hierarchy and set the flags to their initial correct values. Then as long as one is using ->clone(), ->cloneInto() and the AstNode constructor (with children passed to it) to modify the tree, the flags will be kept in sync automatically. On the other hand if we are modifying the children list of an existing node, we may need to call node->fixup_hierarchy_flags() to do a localized fixup. That fixup will update the flags on the node's children, and will propagate the change down the tree if necessary. clone() doesn't always retain the flags of the subtree being cloned. It will produce a tree with a consistent setting of the flags, but the root doesn't have in_param/in_lvalue set unless it's intrinsic to the type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make sure the cloned subtree has the flags consistent with the new placement in a hierarchy. Add asserts to make sure the old and new way of determining the flags agree.
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Commits on Sep 27, 2023
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Merge pull request YosysHQ#3955 from nakengelhardt/nak/show_use_dot_f…
…or_aliases show: use dot for wire aliases instead of BUF
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Merge pull request YosysHQ#3957 from YosysHQ/ver_def_param
Verific: add default parameters to modules
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Commits on Sep 28, 2023
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Fix assertion to what it should be per Andy's comments.
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Merge pull request YosysHQ#3813 from povik/ast-simplify-work-vol2
ast/simplify: Remove in_lvalue/in_param simplify() parameters
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sim: Add -noinitstate option and handle non-cosim initstate
This adds the -noinitstate option which is required to simulate counterexamples to induction with yw-cosim. Also add handling for $initstate cells for non-co-simulation.
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Commits on Sep 29, 2023
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simplify: Avoid calling fixup_hierarchy_flags on nullptr
Compiling on GCC hid this bug as it optimized the nullptr call away as undefined behavior, but running the SBY tests with a clang build hits this error.
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Commits on Sep 30, 2023
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Commits on Oct 2, 2023
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Merge pull request YosysHQ#3959 from rmlarsen/decode_string
Speed up RTLIL::Const::decode_string by 1.7x.
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Speed up simplemap_map by 11.6x by directly inserting the cell source…
… attribute in the new object's 'attributes' map instead of calling set_attr_pool to create a new pool and then copying that. Based on a suggestion by Martin Poviser in a comment on YosysHQ#3959
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Speed up OptMergePass by 1.7x.
The main speedup comes from swithing from using a SHA1 hash to std::hash<std::string>. There is no need to use an expensive cryptographic hash for fingerprinting in this context.
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Commits on Oct 3, 2023
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Speed up stringf / vstringf by 1.8x.
The main speedup is accomplished by avoiding a heap allocation in the common case where the final string length is less than 128. Inlining stringf & vstringf adds an additional improvement.
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Merge pull request YosysHQ#3978 from jix/fix-sva-test
Fix sva_value_change_changed test for updated verific
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Revert changes to celltypes.h. Use dict instead of std::unordered_map…
… and most hash function for uint64_t to hashlib.h to support this.
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Explicitly use uint64_t as the type of fingerprint to avoid type mism…
…atch with some compilers.
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Merge pull request YosysHQ#3977 from YosysHQ/lofty/gowin-dff
gowin: fix abc9 attributes and specify blocks
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booth: Fix vacancy check when summing down result
In commit fedd122 ("booth: Move away from explicit `Wire` pointers") a bug was introduced when checking for vacant slots in arrays holding some intermediate results. Non-wire SigBit values were taken to imply a vacant slot, but actually a constant one can make its way into those results, if the multiplier cell configuration is just right. Fix the vacancy check to address the bug.
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Merge pull request YosysHQ#3982 from povik/booth-fix
booth: Fix vacancy check when summing down result
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sim: Change clocked read port suggestion to
memory_nordff
`memory_nordff` has the advantage that it can be called just ahead of the simulation step no matter whether the clocked read port has been inferred or was explicitly instantiated in a flow.
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Instead of silently missimulating, error out when there are processes found in the simulation hierarchy.
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Merge pull request YosysHQ#3984 from YosysHQ/module_hdlname
verific: save original module name
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Fix translation bug: The old code really checks for the presense of a…
… node, not an edge in glift and flatten. Add back statement that inserts nodes in order in opt_expr.cc.
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Get rid of double lookup in TopoSort::node(). This speeds up typical …
…TopoSort time overall by ~10%.
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Merge pull request YosysHQ#3988 from YosysHQ/micko/fix_leak
Fix readline/editline memory leak
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write_verilog: avoid emitting empty cases.
The Verilog grammar does not allow an empty case. Most synthesis tools are quite permissive about this, but Quartus is not. This causes problems for amaranth with Quartus (see amaranth-lang/amaranth#931).
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Merge pull request YosysHQ#3992 from YosysHQ/empty-case-fix
write_verilog: avoid emitting empty cases.
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Merge pull request YosysHQ#3998 from jix/verific-fix-norename
verific: Use CellBaseName to identify top modules
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Fix name confusion which was making the test look into the vendor's cell blackbox rather than into the synthesis results.
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Merge pull request YosysHQ#4001 from YosysHQ/vhdl_arch
Preserve VHDL architecture name in attribute
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peepopt: Drop unused 'initbits' code
Drop code that was once used by the 'dffmux' pattern but now is unused after that pattern has been obsoleted by the 'opt_dff' pass.
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peepopt: Support shift amounts zero-padded from below
The `opt_expr` pass running before `peepopt` can interfere with the detection of a shiftmul pattern due to some of the bottom bits of the shift amount being replaced with constant zero. Extend the detection to cover those situations as well.
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peepopt: Add left-shift 'shiftmul' variant
Add a separate shiftmul pattern to match on left shifts which implement demuxing. This mirrors the right shift pattern matcher but is probably best kept separate instead of merging the two into a single matcher. In any case the diff of the two matchers should be easily readable.
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Merge pull request YosysHQ#3986 from povik/sim-ui-fixes
Slightly improve `sim` UI
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Merge pull request YosysHQ#4003 from povik/pp3-test-fix
quicklogic: Fix pp3 `dffs` test
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Merge pull request YosysHQ#3946 from rmlarsen/toposort
Speed up TopoSort by 2.7-3.3x.
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verific: import attributes on ports
Co-authored-by: Miodrag Milanović <[email protected]>
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cxxrtl: export wire attributes through the C API.
Co-authored-by: Charlotte <[email protected]>
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Merge pull request YosysHQ#4019 from YosysHQ/lofty/abc9-by-default
ice40, ecp5: enable ABC9 by default
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Merge pull request YosysHQ#4020 from YosysHQ/revert-4019-lofty/abc9-b…
…y-default Revert "ice40, ecp5: enable ABC9 by default"
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peepopt: fix and refactor
shiftadd
- moved all selection and filtering logic to the match block - applied less-verbose code suggestions - removed constraint on number of bits in shift-amount - added check for possible wrap-arround in the operation
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test: add tests for
shiftadd
andshiftmul
This expands the part-select tests with one additional module. It specifically tests the different variants of the `peepopt` optimizations `shiftadd` and `shiftmul`. Not all these cases are actually transformed using `shiftadd`, including them also checks if the correct variants are rejected.
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Merge pull request YosysHQ#4015 from YosysHQ/log_verific
Change Verific log callback API
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Merge pull request YosysHQ#4008 from nakengelhardt/mem_libmap_data_attr
memory_libmap: look for ram_style attributes on surrounding signals
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cli: Cleanups for tcl argument handling
* Keep the previous behavior when no tcl script is used * Do not treat "-" as a flag but as a positional argument * Keep including <unistd.h> as it's also used for other functions (at least for the emscripten build) * Move the custom getopt implementation into the Yosys namespace to avoid potential collisions
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Merge pull request YosysHQ#3883 from phsauter/peepopt-shiftadd
peepopt: Add `shiftadd` pattern
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synth_lattice: Merge NOT gates on DFF control signals
`dfflegalize` will emit NOT gates to drive control signals on flip-flops when mapping to supported flip-flop polarities. Typically in a design this will produce a number of NOT gates driven by the same signal. For one reason or another ABC doesn't fully cancel this redundancy during LUT mapping. Insert an explicit `opt_merge` pass to improve synthesis QoR.
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synth_lattice: Optimize flip-flop memories better
After `memory_map` maps memories to flip-flops we need to let `opt` remove undef muxes, otherwise we block enable/reset signal inference by `opt_dff` which is in detriment to QoR.
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Merge pull request YosysHQ#4027 from YosysHQ/achronix_typo
Fix typo in help message (Acrhonix -> Achronix)
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Merge pull request YosysHQ#3973 from anonkey/master
cli(tcl): add ability to pass argument to tcl script from cli
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Merge pull request YosysHQ#4028 from povik/cmp2softlogic
synth_lattice: Optionally do constant comparisons in soft logic
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Merge pull request YosysHQ#4022 from povik/machxo3-qor-work
MachXO3 QoR improvements
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Merge pull request YosysHQ#4029 from YosysHQ/lofty/abc9-again
ice40, ecp5, gowin: enable ABC9 by default
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Merge pull request YosysHQ#4032 from YosysHQ/lofty/gowin-abc9-oopsie
gowin: fix typo
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Merge pull request YosysHQ#4037 from YosysHQ/lofty/ice40-abc9-oopsie
ice40: fix -noabc9
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Merge pull request #7 from thiskappaisgrey/patch-1
Add `#include <assert.h>` to make it build
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Merge pull request #8 from thiskappaisgrey/thiskappaisgrey/lakeroad-b…
…ackend-tests Add a new test for the not cell.
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Allow
write_lakeroad
backend to write output to file instead of std……out. (#9) * Add code to write_lakeroad to file instead of stdout * Fix a bug for writing to stdout as well * Add suggested code
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