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Add Lakeroad egglog backend #4

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Commits on Sep 3, 2023

  1. Add RUN lines

    gussmith23 committed Sep 3, 2023
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Commits on Sep 4, 2023

  1. More work

    gussmith23 committed Sep 4, 2023
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  4. Update test

    gussmith23 committed Sep 4, 2023
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  5. sim: Add print support

    povik committed Sep 4, 2023
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  7. memlib.md: Fix typo

    povik committed Sep 4, 2023
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Commits on Sep 5, 2023

  1. Bump version

    github-actions[bot] committed Sep 5, 2023
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  2. Release version 0.33

    mmicko committed Sep 5, 2023
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  3. Next dev cycle

    mmicko committed Sep 5, 2023
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  6. ast: Substitute rvalues when parsing out print arguments

    Apply the local substitutions stemming from process context when parsing
    out format arguments to `$display` or other statements.
    povik committed Sep 5, 2023
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Commits on Sep 6, 2023

  1. Bump version

    github-actions[bot] committed Sep 6, 2023
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  2. sv: support assignments within expressions

    - Add support for assignments within expressions, e.g., `x[y++] = z;` or
      `x = (y *= 2) - 1;`. The logic is handled entirely within the parser
      by injecting statements into the current procedural block.
    - Add support for pre-increment/decrement statements, which are
      behaviorally equivalent to post-increment/decrement statements.
    - Fix non-standard attribute position used for post-increment/decrement
      statements.
    zachjs committed Sep 6, 2023
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  3. xprop: Fix polarity errors and generate hdlnames

    * Fixes a non-deterministic polarity error for $eqx/$nex cells
    * Fixes a deterministic polarity error for $_NOR_ and $_ORNOT_ cells
    * Generates hdlnames when xprop is run after flatten
    jix committed Sep 6, 2023
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Commits on Sep 7, 2023

  1. Bump version

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Commits on Sep 8, 2023

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Commits on Sep 10, 2023

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Commits on Sep 11, 2023

  1. Update ABC to latest

    mmicko committed Sep 11, 2023
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  2. Merge pull request YosysHQ#3915 from povik/sim-print

    sim: Add print support
    povik authored Sep 11, 2023
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  3. Merge pull request YosysHQ#3918 from povik/print-sampling-fix

    ast: Substitute rvalues when parsing out print arguments
    povik authored Sep 11, 2023
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Commits on Sep 12, 2023

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  2. Merge pull request YosysHQ#3926 from YosysHQ/update_abc2

    Update ABC to latest
    mmicko authored Sep 12, 2023
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  3. Merge pull request YosysHQ#3927 from YosysHQ/verific_memory

    verific - respect order of read and write for rams
    mmicko authored Sep 12, 2023
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  4. Merge pull request YosysHQ#3892 from QuantamHD/dont_use

    abc: Exposes dont_use flag in ABC
    mmicko authored Sep 12, 2023
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  5. mem: Fix index confusion in write port merging

    Fix mistaking the read-port and write-port indices for each other when
    we are adding the partial transparency emulation to be able to merge two
    write ports.
    povik committed Sep 12, 2023
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  6. fmt: Fix C++ string assertion when buf is empty

    Signed-off-by: gatecat <[email protected]>
    gatecat committed Sep 12, 2023
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  7. Merge pull request YosysHQ#3928 from povik/mem-wr-merge-transpemu-fix

    mem: Fix index confusion in write port merging
    povik authored Sep 12, 2023
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  8. Merge pull request YosysHQ#3929 from YosysHQ/gatecat/fmt-fix

    fmt: Fix C++ string assertion when buf is empty
    povik authored Sep 12, 2023
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Commits on Sep 13, 2023

  1. Bump version

    github-actions[bot] committed Sep 13, 2023
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  2. Basic support for tag primitives

    mmicko authored and jix committed Sep 13, 2023
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  3. unescape string tag attribute

    mmicko authored and jix committed Sep 13, 2023
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  4. Support import of $future_ff

    mmicko authored and jix committed Sep 13, 2023
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  5. Initial dft_tag implementation

    This is still missing a mode to rewrite $overwrite_tag and $original_tag
    by injecting $set_tag and $get_tag in the right places. It's also
    missing bit-precise propagation models for shifts and arithmetic and
    requires the design to be flattened.
    jix committed Sep 13, 2023
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  7. Run future as part of prep

    jix committed Sep 13, 2023
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  8. dft_tag: Implement $overwrite_tag and $original_tag

    This does not correctly handle an `$overwrite_tag` on a module output,
    but since we currently require the user to flatten the design for
    cross-module dft, this cannot be observed from within the design, only
    by manually inspecting the signals in the design.
    jix committed Sep 13, 2023
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  11. Merge pull request YosysHQ#3903 from jix/dft-future_ff

    Basic support for tag primitives and `$future_ff`
    mmicko authored Sep 13, 2023
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  12. Merge pull request YosysHQ#3931 from whitequark/update-abc

    Update ABC for WASI support
    mmicko authored Sep 13, 2023
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Commits on Sep 14, 2023

  1. Bump version

    github-actions[bot] committed Sep 14, 2023
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Commits on Sep 15, 2023

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Commits on Sep 18, 2023

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  4. Merge pull request YosysHQ#3924 from andyfox-rushc/master

    multpass -- create Booth Encoded multipliers for
    povik authored Sep 18, 2023
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Commits on Sep 19, 2023

  1. Bump version

    github-actions[bot] committed Sep 19, 2023
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  5. Merge pull request YosysHQ#3943 from YosysHQ/verific_lineinfo

    Set src attribute for verific with full info
    mmicko authored Sep 19, 2023
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Commits on Sep 20, 2023

  1. Bump version

    github-actions[bot] committed Sep 20, 2023
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  2. Merge pull request YosysHQ#3920 from zachjs/asgn-expr

    sv: support assignments within expressions
    povik authored Sep 20, 2023
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  3. Merge pull request YosysHQ#3930 from povik/verific-test-memsemantics

    verific: Add test of accurate semantics in memory inference
    povik authored Sep 20, 2023
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  4. Speed up TopoSort. The main sorting algorithm implementation in TopoS…

    …ort::sort_worker is 11-12x faster. Overall, the complete sequence of building the graph and sorting is about 2.5-3x faster. The overall impact in e.g. the replace_const_cells optimization pass is a ~25% speedup. End-to-end impact on our synthesis flow is about 3%.
    rmlarsen committed Sep 20, 2023
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  5. Remove extraneous "public:".

    rmlarsen committed Sep 20, 2023
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Commits on Sep 21, 2023

  1. rtlil: Speeds up Yosys by 17%

    This PR speeds up by roughly 17% across a wide spectrum of designs
    tested at Google. Particularly for the mux generation pass.
    
    Co-authored-by: Rasmus Larsen <[email protected]>
    Signed-off-by: Ethan Mahintorabi <[email protected]>
    2 people authored and whitequark committed Sep 21, 2023
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  2. Speed up the autoname pass by 3x. (YosysHQ#3945)

    * Speed up the autoname pass by 2x. This is accomplished by only constructing IdString objects for plain strings that have a higher score.
    
    * Defer creating IdStrings even further. This increases the speedup to 3x.
    rmlarsen authored Sep 21, 2023
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Commits on Sep 22, 2023

  1. Bump version

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Commits on Sep 25, 2023

  1. booth: Move away from explicit Wire pointers

    To represent intermediate signals use the `SigBit`/`SigSpec` classes as
    is customary in the Yosys codebase. Do not pass around `Wire` pointers
    unless we have special reason to.
    povik committed Sep 25, 2023
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  3. booth: Streamline the low-level circuit emission

    For the basic single-bit operations, opt for gate cells (`$_AND_` etc.)
    instead of the coarse cells (`$and` etc.). For the emission of cells
    move to the conventional module methods (`module->addAndGate`) away
    from the local helpers. While at it, touch on the surrounding code.
    povik committed Sep 25, 2023
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  7. booth: Make more use of appropriate helpers

    Use the `addFa` helper, do not misuse `new_id` and make other changes
    to the transformation code.
    povik committed Sep 25, 2023
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  8. booth: Improve user interface

    povik committed Sep 25, 2023
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Commits on Sep 26, 2023

  1. ast/simplify: Make tweaks in advance of big in_lvalue/in_param change

    The following commit will replace the way in_lvalue/in_param is being
    tracked in the simplify code. Make tweaks in advance so that it will
    be easier to make the old way and the new way agree.
    
    These changes all should be innocuous.
    povik committed Sep 26, 2023
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  2. ast/simplify: Make in_lvalue/in_param into props of AST nodes

    Instead of passing around in_lvalue/in_param flags to simplify, we make
    the flags into properties of the AST nodes themselves. After the tree
    is first parsed, we once do
    
      ast->fixup_hierarchy_flags(true)
    
    to walk the full hierarchy and set the flags to their initial correct
    values. Then as long as one is using ->clone(), ->cloneInto() and the
    AstNode constructor (with children passed to it) to modify the tree, the
    flags will be kept in sync automatically. On the other hand if we are
    modifying the children list of an existing node, we may need to call
    
      node->fixup_hierarchy_flags()
    
    to do a localized fixup. That fixup will update the flags on the node's
    children, and will propagate the change down the tree if necessary.
    
    clone() doesn't always retain the flags of the subtree being cloned. It
    will produce a tree with a consistent setting of the flags, but the
    root doesn't have in_param/in_lvalue set unless it's intrinsic to the
    type of node being cloned (e.g. AST_PARAMETER). cloneInto() will make
    sure the cloned subtree has the flags consistent with the new placement
    in a hierarchy.
    
    Add asserts to make sure the old and new way of determining the flags
    agree.
    povik committed Sep 26, 2023
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Commits on Sep 27, 2023

  1. Bump version

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  2. Merge pull request YosysHQ#3955 from nakengelhardt/nak/show_use_dot_f…

    …or_aliases
    
    show: use dot for wire aliases instead of BUF
    povik authored Sep 27, 2023
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  4. Merge pull request YosysHQ#3957 from YosysHQ/ver_def_param

    Verific: add default parameters to modules
    mmicko authored Sep 27, 2023
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Commits on Sep 28, 2023

  1. Bump version

    github-actions[bot] committed Sep 28, 2023
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  3. booth: Fix assertion

    Fix assertion to what it should be per Andy's comments.
    povik committed Sep 28, 2023
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  4. booth: Cut down the test

    Cut the test down from taking ~25 s to ~3 s.
    povik committed Sep 28, 2023
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  5. Merge pull request YosysHQ#3813 from povik/ast-simplify-work-vol2

    ast/simplify: Remove in_lvalue/in_param simplify() parameters
    povik authored Sep 28, 2023
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  6. sim: Add -noinitstate option and handle non-cosim initstate

    This adds the -noinitstate option which is required to simulate
    counterexamples to induction with yw-cosim. Also add handling for
    $initstate cells for non-co-simulation.
    jix committed Sep 28, 2023
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Commits on Sep 29, 2023

  1. Unflip i and j.

    rmlarsen committed Sep 29, 2023
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  2. simplify: Avoid calling fixup_hierarchy_flags on nullptr

    Compiling on GCC hid this bug as it optimized the nullptr call away as
    undefined behavior, but running the SBY tests with a clang build hits
    this error.
    jix committed Sep 29, 2023
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Commits on Sep 30, 2023

  1. Bump version

    github-actions[bot] committed Sep 30, 2023
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Commits on Oct 2, 2023

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  2. Merge pull request YosysHQ#3959 from rmlarsen/decode_string

    Speed up RTLIL::Const::decode_string by 1.7x.
    povik authored Oct 2, 2023
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  5. Ignore emacs auto-save files.

    rmlarsen authored and Ravenslofty committed Oct 2, 2023
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  6. Speed up simplemap_map by 11.6x by directly inserting the cell source…

    … attribute in the new object's 'attributes' map instead of calling set_attr_pool to create a new pool and then copying that. Based on a suggestion by Martin Poviser in a comment on YosysHQ#3959
    rmlarsen authored and Ravenslofty committed Oct 2, 2023
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  7. Revert formatting changes.

    rmlarsen authored and Ravenslofty committed Oct 2, 2023
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  8. Revert changes to techmap.cc.

    rmlarsen authored and Ravenslofty committed Oct 2, 2023
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  9. Speed up OptMergePass by 1.7x.

    The main speedup comes from swithing from using a SHA1 hash to std::hash<std::string>. There is no need to use an expensive cryptographic hash for fingerprinting in this context.
    rmlarsen committed Oct 2, 2023
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  10. Undo formatting change.

    rmlarsen committed Oct 2, 2023
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Commits on Oct 3, 2023

  1. Bump version

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  2. Speed up stringf / vstringf by 1.8x.

    The main speedup is accomplished by avoiding a heap allocation in the common case where the final string length is less than 128. Inlining stringf & vstringf adds an additional improvement.
    rmlarsen authored and Ravenslofty committed Oct 3, 2023
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  3. Update comment.

    rmlarsen authored and Ravenslofty committed Oct 3, 2023
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  4. Remove local modifications.

    rmlarsen authored and Ravenslofty committed Oct 3, 2023
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  5. Fix compiler warnings from GCC.

    rmlarsen authored and Ravenslofty committed Oct 3, 2023
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  7. Merge pull request YosysHQ#3978 from jix/fix-sva-test

    Fix sva_value_change_changed test for updated verific
    mmicko authored Oct 3, 2023
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  11. Revert changes to celltypes.h. Use dict instead of std::unordered_map…

    … and most hash function for uint64_t to hashlib.h to support this.
    rmlarsen committed Oct 3, 2023
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  12. Explicitly use uint64_t as the type of fingerprint to avoid type mism…

    …atch with some compilers.
    rmlarsen committed Oct 3, 2023
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Commits on Oct 4, 2023

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  2. Merge pull request YosysHQ#3977 from YosysHQ/lofty/gowin-dff

    gowin: fix abc9 attributes and specify blocks
    Ravenslofty authored Oct 4, 2023
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  3. booth: Fix vacancy check when summing down result

    In commit fedd122 ("booth: Move away from explicit `Wire` pointers")
    a bug was introduced when checking for vacant slots in arrays holding
    some intermediate results. Non-wire SigBit values were taken to imply
    a vacant slot, but actually a constant one can make its way into those
    results, if the multiplier cell configuration is just right. Fix the
    vacancy check to address the bug.
    povik committed Oct 4, 2023
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Commits on Oct 5, 2023

  1. Merge pull request YosysHQ#3982 from povik/booth-fix

    booth: Fix vacancy check when summing down result
    mmicko authored Oct 5, 2023
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  2. Release version 0.34

    mmicko committed Oct 5, 2023
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  3. Next dev cycle

    mmicko committed Oct 5, 2023
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  4. mingw build fix

    mmicko committed Oct 5, 2023
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  9. sim: Change clocked read port suggestion to memory_nordff

    `memory_nordff` has the advantage that it can be called just ahead of
    the simulation step no matter whether the clocked read port has been
    inferred or was explicitly instantiated in a flow.
    povik committed Oct 5, 2023
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  10. sim: s/instanced/instantiated/

    povik committed Oct 5, 2023
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  11. sim: Bail on processes

    Instead of silently missimulating, error out when there are processes
    found in the simulation hierarchy.
    povik committed Oct 5, 2023
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  12. Merge pull request YosysHQ#3984 from YosysHQ/module_hdlname

    verific: save original module name
    mmicko authored Oct 5, 2023
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  14. Add back newline.

    rmlarsen committed Oct 5, 2023
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Commits on Oct 6, 2023

  1. Fix translation bug: The old code really checks for the presense of a…

    … node, not an edge in glift and flatten.
    
    Add back statement that inserts nodes in order in opt_expr.cc.
    rmlarsen committed Oct 6, 2023
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  2. Bump version

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  4. ast/simplify: Remove unused in_param code

    povik authored and zachjs committed Oct 6, 2023
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  6. Get rid of double lookup in TopoSort::node(). This speeds up typical …

    …TopoSort time overall by ~10%.
    rmlarsen committed Oct 6, 2023
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Commits on Oct 7, 2023

  1. Bump version

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  3. Merge pull request YosysHQ#3988 from YosysHQ/micko/fix_leak

    Fix readline/editline memory leak
    Ravenslofty authored Oct 7, 2023
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  4. write_verilog: avoid emitting empty cases.

    The Verilog grammar does not allow an empty case.  Most synthesis tools
    are quite permissive about this, but Quartus is not.  This causes
    problems for amaranth with Quartus (see amaranth-lang/amaranth#931).
    wanda-phi committed Oct 7, 2023
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  5. Add Xor

    gussmith23 committed Oct 7, 2023
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  6. Add shr

    gussmith23 committed Oct 7, 2023
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Commits on Oct 8, 2023

  1. Merge pull request YosysHQ#3992 from YosysHQ/empty-case-fix

    write_verilog: avoid emitting empty cases.
    Ravenslofty authored Oct 8, 2023
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Commits on Oct 9, 2023

  1. Bump version

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Commits on Oct 10, 2023

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Commits on Oct 11, 2023

  1. Merge pull request YosysHQ#3998 from jix/verific-fix-norename

    verific: Use CellBaseName to identify top modules
    mmicko authored Oct 11, 2023
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Commits on Oct 12, 2023

  1. Bump version

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  3. quicklogic: Fix pp3 dffs test

    Fix name confusion which was making the test look into the vendor's cell
    blackbox rather than into the synthesis results.
    povik committed Oct 12, 2023
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Commits on Oct 13, 2023

  1. Merge pull request YosysHQ#4001 from YosysHQ/vhdl_arch

    Preserve VHDL architecture name in attribute
    mmicko authored Oct 13, 2023
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  2. Update abc

    mmicko committed Oct 13, 2023
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Commits on Oct 14, 2023

  1. Bump version

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Commits on Oct 16, 2023

  1. peepopt: Drop unused 'initbits' code

    Drop code that was once used by the 'dffmux' pattern but now is unused
    after that pattern has been obsoleted by the 'opt_dff' pass.
    povik committed Oct 16, 2023
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  2. peepopt: Clean up 'shiftmul' a bit

    No functional change intended.
    povik committed Oct 16, 2023
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  4. peepopt: Support shift amounts zero-padded from below

    The `opt_expr` pass running before `peepopt` can interfere with the
    detection of a shiftmul pattern due to some of the bottom bits of the
    shift amount being replaced with constant zero. Extend the detection to
    cover those situations as well.
    povik committed Oct 16, 2023
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  5. peepopt: Add left-shift 'shiftmul' variant

    Add a separate shiftmul pattern to match on left shifts which implement
    demuxing. This mirrors the right shift pattern matcher but is probably
    best kept separate instead of merging the two into a single matcher.
    In any case the diff of the two matchers should be easily readable.
    povik committed Oct 16, 2023
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  8. pmgen: Fix sample syntax

    povik committed Oct 16, 2023
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  11. Merge pull request YosysHQ#3986 from povik/sim-ui-fixes

    Slightly improve `sim` UI
    clairexen authored Oct 16, 2023
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Commits on Oct 17, 2023

  1. Bump version

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  2. Merge pull request YosysHQ#4003 from povik/pp3-test-fix

    quicklogic: Fix pp3 `dffs` test
    Ravenslofty authored Oct 17, 2023
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  3. Merge pull request YosysHQ#3946 from rmlarsen/toposort

    Speed up TopoSort by 2.7-3.3x.
    Ravenslofty authored Oct 17, 2023
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Commits on Oct 19, 2023

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Commits on Oct 20, 2023

  1. verific: import attributes on ports

    Co-authored-by: Miodrag Milanović <[email protected]>
    nakengelhardt and mmicko committed Oct 20, 2023
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Commits on Oct 24, 2023

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Commits on Oct 25, 2023

  1. cxxrtl: export wire attributes through the C API.

    Co-authored-by: Charlotte <[email protected]>
    whitequark and charlottia committed Oct 25, 2023
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Commits on Oct 26, 2023

  1. Bump version

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Commits on Oct 30, 2023

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Commits on Nov 1, 2023

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Commits on Nov 3, 2023

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  4. Merge pull request YosysHQ#4019 from YosysHQ/lofty/abc9-by-default

    ice40, ecp5: enable ABC9 by default
    Ravenslofty authored Nov 3, 2023
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  6. Merge pull request YosysHQ#4020 from YosysHQ/revert-4019-lofty/abc9-b…

    …y-default
    
    Revert "ice40, ecp5: enable ABC9 by default"
    Ravenslofty authored Nov 3, 2023
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Commits on Nov 4, 2023

  1. Bump version

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Commits on Nov 6, 2023

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  2. peepopt: fix and refactor shiftadd

    - moved all selection and filtering logic to the match block
    - applied less-verbose code suggestions
    - removed constraint on number of bits in shift-amount
    - added check for possible wrap-arround in the operation
    phsauter committed Nov 6, 2023
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  4. test: add tests for shiftadd and shiftmul

    This expands the part-select tests with one additional module.
    It specifically tests the different variants of the `peepopt`
    optimizations `shiftadd` and `shiftmul`.
    Not all these cases are actually transformed using `shiftadd`,
    including them also checks if the correct variants are rejected.
    phsauter committed Nov 6, 2023
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  5. Merge pull request YosysHQ#4015 from YosysHQ/log_verific

    Change Verific log callback API
    mmicko authored Nov 6, 2023
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  6. Merge pull request YosysHQ#4008 from nakengelhardt/mem_libmap_data_attr

    memory_libmap: look for ram_style attributes on surrounding signals
    nakengelhardt authored Nov 6, 2023
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  8. cli: Cleanups for tcl argument handling

    * Keep the previous behavior when no tcl script is used
    * Do not treat "-" as a flag but as a positional argument
    * Keep including <unistd.h> as it's also used for other functions (at
      least for the emscripten build)
    * Move the custom getopt implementation into the Yosys namespace to
      avoid potential collisions
    jix committed Nov 6, 2023
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Commits on Nov 7, 2023

  1. Release version 0.35

    mmicko committed Nov 7, 2023
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  2. Next dev cycle

    mmicko committed Nov 7, 2023
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  3. Merge pull request YosysHQ#3883 from phsauter/peepopt-shiftadd

    peepopt: Add `shiftadd` pattern
    nakengelhardt authored Nov 7, 2023
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  4. synth_lattice: Merge NOT gates on DFF control signals

    `dfflegalize` will emit NOT gates to drive control signals on flip-flops
    when mapping to supported flip-flop polarities. Typically in a design
    this will produce a number of NOT gates driven by the same signal. For
    one reason or another ABC doesn't fully cancel this redundancy during
    LUT mapping. Insert an explicit `opt_merge` pass to improve synthesis
    QoR.
    povik committed Nov 7, 2023
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  5. synth_lattice: Optimize flip-flop memories better

    After `memory_map` maps memories to flip-flops we need to let `opt`
    remove undef muxes, otherwise we block enable/reset signal inference by
    `opt_dff` which is in detriment to QoR.
    povik committed Nov 7, 2023
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Commits on Nov 8, 2023

  1. Bump version

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Commits on Nov 13, 2023

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  4. Merge pull request YosysHQ#4027 from YosysHQ/achronix_typo

    Fix typo in help message (Acrhonix -> Achronix)
    nakengelhardt authored Nov 13, 2023
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  6. Merge pull request YosysHQ#3973 from anonkey/master

    cli(tcl): add ability to pass argument to tcl script from cli
    jix authored Nov 13, 2023
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  7. Merge pull request YosysHQ#4028 from povik/cmp2softlogic

    synth_lattice: Optionally do constant comparisons in soft logic
    nakengelhardt authored Nov 13, 2023
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  8. Merge pull request YosysHQ#4022 from povik/machxo3-qor-work

    MachXO3 QoR improvements
    nakengelhardt authored Nov 13, 2023
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  9. Merge pull request YosysHQ#4029 from YosysHQ/lofty/abc9-again

    ice40, ecp5, gowin: enable ABC9 by default
    nakengelhardt authored Nov 13, 2023
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Commits on Nov 14, 2023

  1. Bump version

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  4. gowin: fix typo

    Ravenslofty committed Nov 14, 2023
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Commits on Nov 15, 2023

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Commits on Nov 17, 2023

  1. ice40: fix -noabc9

    Ravenslofty committed Nov 17, 2023
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Commits on Nov 18, 2023

  1. Bump version

    github-actions[bot] committed Nov 18, 2023
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Commits on Nov 20, 2023

  1. Merge pull request #7 from thiskappaisgrey/patch-1

    Add `#include <assert.h>` to make it build
    gussmith23 authored Nov 20, 2023
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  4. Change to new syntax

    gussmith23 committed Nov 20, 2023
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  5. Fix test

    gussmith23 committed Nov 20, 2023
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Commits on Dec 6, 2023

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Commits on Dec 8, 2023

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Commits on Dec 12, 2023

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  3. Merge pull request #8 from thiskappaisgrey/thiskappaisgrey/lakeroad-b…

    …ackend-tests
    
    Add a new test for the not cell.
    gussmith23 authored Dec 12, 2023
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Commits on Dec 17, 2023

  1. Allow write_lakeroad backend to write output to file instead of std…

    …out. (#9)
    
    * Add code to write_lakeroad to file instead of stdout
    
    * Fix a bug for writing to stdout as well
    
    * Add suggested code
    thiskappaisgrey authored Dec 17, 2023
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Commits on Jan 31, 2024

  1. notes from yosys meeting

    gussmith23 committed Jan 31, 2024
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Commits on Feb 5, 2024

  1. Add note on bug

    gussmith23 committed Feb 5, 2024
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  2. Don't sigmap, as it causes a loop.

    See #10
    gussmith23 committed Feb 5, 2024
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  3. Don't techmap

    gussmith23 committed Feb 5, 2024
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