Add simple mux test case - fails because of not

uwsampl · Dec 8, 2023 · d9aec27 · d9aec27
1 parent 9e0a5b1
commit d9aec27
Showing 1 changed file with 14 additions and 0 deletions.
diff --git a/backends/lakeroad/tests/simple-mux.sv b/backends/lakeroad/tests/simple-mux.sv
@@ -0,0 +1,14 @@
+// RUN: "$YOSYS" -p 'read_verilog -sv %s; prep -top test; pmuxtree; write_lakeroad'
+module test(input [2:0] a, output [2:0] out);
+  // assign out = ~ a;
+  always_comb begin
+	  case (a)
+		  2'b01: out = 2'b10;
+		  2'b00: out = 2'b10;
+		  2'b10: out = 2'b00;
+		  2'b11: out = 2'b01;
+		  default: out = 2'b01;
+	  endcase
+  end
+endmodule
+