Change the tests to the other format

backends/lakeroad/tests/simple-mux.sv → backends/lakeroad/tests/simple-mux.ys

@@ -1,5 +1,4 @@
-// RUN: "$YOSYS" -p 'read_verilog -sv %s; prep -top test; pmuxtree;\
-// RUN: proc; opt; memory; opt; techmap; opt; abc; opt; write_lakeroad'
+read_verilog -sv <<EOF
 module test(input [2:0] a, output [2:0] out);
   // assign out = ~ a;
   always_comb begin
@@ -12,4 +11,10 @@ module test(input [2:0] a, output [2:0] out);
 	  endcase
   end
 endmodule
-
+EOF
+# Optimize out the mux to simple gates.
+prep -top test; pmuxtree;
+proc; opt; memory; opt;
+techmap; opt;
+abc; opt;
+write_lakeroad

backends/lakeroad/tests/simple-mux1.ys

@@ -0,0 +1,15 @@
+read_verilog -sv <<EOF
+/* This module is generated by using "simple-mux.ys" + "write_verilog -noattr simple-mux.v". Delete this once you find the problem(most likely due to attributes). */
+module test(a, out);
+  wire _0_;
+  input [2:0] a;
+  wire [2:0] a;
+  output [2:0] out;
+  wire [2:0] out;
+  assign _0_ = a[0] & a[1];
+  assign out[1] = ~(a[1] | a[2]);
+  assign out[0] = a[2] | _0_;
+  assign out[2] = 1'h0;
+endmodule
+EOF
+write_lakeroad

backends/lakeroad/tests/simple-not.ys

@@ -0,0 +1,6 @@
+read_verilog -sv <<EOF
+module test(input a, output out);
+  assign out = ~ a;
+endmodule
+EOF
+write_lakeroad