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Can SparseTIR support operations other than multiplication and addition?
#101
opened Jul 10, 2024 by
gxiaotian
[Bug] remove_unused_args incompatible with VarUseDefAnalysis in make_packed_api
#98
opened Apr 6, 2023 by
qelk123
[Tracking Issue] Support Axis Union/Intersection
enhancement
New feature or request
help wanted
Extra attention is needed
#72
opened Nov 18, 2022 by
yzh119
3 tasks
[Tracking Issue] Inherit block iter_var from parent blocks
priority-high
#71
opened Nov 15, 2022 by
yzh119
2 tasks
[Discussion] How to efficiently handle branches in the axes dependency tree for sparse buffers.
#69
opened Nov 14, 2022 by
yzh119
[Tracking Issue] Documentation Completion
documentation
Improvements or additions to documentation
#68
opened Nov 14, 2022 by
yzh119
8 tasks
[Tracking Issue] Redesign the internal storage of sparse buffers.
#65
opened Nov 14, 2022 by
yzh119
3 tasks
[Tracking Issue] SparseTIR Compatibility with Software Pipelining and Async Copy
#61
opened Nov 3, 2022 by
yzh119
[Bug] Reverse Cache Read/Write do not consider itervars in outer blocks.
#60
opened Oct 31, 2022 by
yzh119
[Tracking Issue] Using MMA and ldmatrix instrinsics to save shared memory usage
#52
opened Oct 12, 2022 by
yzh119
[Tracking Issue] Add
keep_unit_loop
argument for reverse_cache_read
and reverse_cache_write
#50
opened Oct 9, 2022 by
yzh119
[Bug] ThreadStorageSync pass didn't insert
synthreads
successfullly for cooperative fetching.
#47
opened Oct 7, 2022 by
yzh119
[Tracking Issue] Upstreaming: customized index mapping function in cache read/write
#45
opened Oct 6, 2022 by
yzh119
[Tracking Issue] Specialize buffer value by specifying key value mappings.
#40
opened Sep 28, 2022 by
yzh119
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