fix broken SIMD acceleration on apple silicon

tayloraswift · Jan 31, 2024 · 8dec7c9 · 8dec7c9
1 parent daa6a07
commit 8dec7c9
Showing 1 changed file with 17 additions and 11 deletions.
diff --git a/Sources/LZ77/SIMD16 (ext).swift b/Sources/LZ77/SIMD16 (ext).swift
@@ -4,7 +4,7 @@
 
 import _Builtin_intrinsics.intel
 
-extension SIMD16 where Scalar == UInt8
+extension SIMD16<UInt8>
 {
     func find(_ key:UInt8) -> UInt16
     {
@@ -18,19 +18,25 @@ extension SIMD16 where Scalar == UInt8
 
 #else
 
-extension SIMD16 where Scalar == UInt8
+extension SIMD16<UInt8>
 {
     func find(_ key:UInt8) -> UInt16
     {
-        // (key: 5, vector: (1, 5, 1, 1, 5, 5, 1, 1, 1, 1, 1, 1, 5, 1, 1, 5))
-        let places:SIMD16<UInt8>    =
-            .init(128, 64, 32, 16, 8, 4, 2, 1, 128, 64, 32, 16, 8, 4, 2, 1),
-            match:SIMD16<UInt8>     = places.replacing(with: 0, where: self .!= key)
-        // match: ( 0, 64,  0,  0,  8,  4,  0,  0,  0,  0,  0,  0,  8,  0,  0,  1)
-        let r8:SIMD8<UInt8> =    match.evenHalf |    match.oddHalf,
-            r4:SIMD4<UInt8> =       r8.evenHalf |       r8.oddHalf,
-            r2:SIMD2<UInt8> =       r4.evenHalf |       r4.oddHalf
-        return .init(r2.x) << 8  | .init(r2.y)
+        //  key: 5
+        //  vector:
+        // (1, 5, 1, 1,  5,  5,  1,   1,
+        //  1, 1, 1, 1,  5,  1,  1,   5)
+        let places:SIMD16<UInt8> = .init(
+            1, 2, 4, 8, 16, 32, 64, 128,
+            1, 2, 4, 8, 16, 32, 64, 128)
+        let match:SIMD16<UInt8> = places.replacing(with: 0, where: self .!= key)
+        // match:
+        // (0, 2, 0, 0, 16, 32,  0,   0,
+        //  0, 0, 0, 0, 16,  0,  0, 128)
+        let r8:SIMD8<UInt8> =    match.evenHalf |    match.oddHalf
+        let r4:SIMD4<UInt8> =       r8.evenHalf |       r8.oddHalf
+        let r2:SIMD2<UInt8> =       r4.evenHalf |       r4.oddHalf
+        return .init(r2.y) << 8  | .init(r2.x)
     }
 }