Merge pull request #666 from YruamaLairba/StreamX_improve

Stream x improve

CHANGELOG.md

@@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+- complete and rework Dma Stream API [#666]
+
+[#666]: https://github.com/stm32-rs/stm32f4xx-hal/pull/666
+
 ## [v0.17.1] - 2023-07-24
 
 ### Changed

examples/rtic-serial-dma-rx-idle.rs

@@ -14,10 +14,7 @@
 mod app {
 
  use hal::{
- dma::{
- config::DmaConfig, traits::Stream, traits::StreamISR, PeripheralToMemory, Stream2,
- StreamsTuple, Transfer,
- },
+ dma::{config::DmaConfig, PeripheralToMemory, Stream2, StreamsTuple, Transfer},
  pac::{DMA2, USART1},
  prelude::*,
  rcc::RccExt,
@@ -120,7 +117,7 @@ mod app {
 
  if transfer.is_idle() {
  // Calc received bytes count
- let bytes_count = BUFFER_SIZE - Stream2::<DMA2>::get_number_of_transfers() as usize;
+ let bytes_count = BUFFER_SIZE - transfer.number_of_transfers() as usize;
 
  // Allocate new buffer
  let new_buffer = cx.local.rx_buffer.take().unwrap();
@@ -143,11 +140,11 @@ mod app {
  fn dma2_stream2(mut cx: dma2_stream2::Context) {
  let transfer = &mut cx.shared.rx_transfer;
 
- if Stream2::<DMA2>::get_fifo_error_flag() {
- transfer.clear_fifo_error_interrupt();
+ if transfer.is_fifo_error() {
+ transfer.clear_fifo_error();
  }
- if Stream2::<DMA2>::get_transfer_complete_flag() {
- transfer.clear_transfer_complete_interrupt();
+ if transfer.is_transfer_complete() {
+ transfer.clear_transfer_complete();
 
  // Buffer is full, but no IDLE received!
  // You can process this data or discard data (ignore transfer complete interrupt and wait IDLE).

examples/rtic-spi-slave-dma.rs

@@ -9,8 +9,8 @@ mod app {
  use embedded_hal::spi::{Mode, Phase, Polarity};
  use hal::{
  dma::{
- config::DmaConfig, traits::StreamISR, MemoryToPeripheral, PeripheralToMemory, Stream0,
- Stream5, StreamsTuple, Transfer,
+ config::DmaConfig, MemoryToPeripheral, PeripheralToMemory, Stream0, Stream5,
+ StreamsTuple, Transfer,
  },
  gpio::{gpioc::PC13, GpioExt, Output, PushPull},
  pac::{DMA1, SPI3},
@@ -138,50 +138,40 @@ mod app {
  // The led lights up if the first byte we receive is a 1, it turns off otherwise
  #[task(binds = DMA1_STREAM0, shared = [rx_transfer, led], local = [rx_buffer])]
  fn on_receiving(cx: on_receiving::Context) {
- let on_receiving::Context { mut shared, local } = cx;
- if Stream0::<DMA1>::get_fifo_error_flag() {
- shared
- .rx_transfer
- .lock(|spi_dma| spi_dma.clear_fifo_error_interrupt());
- }
- if Stream0::<DMA1>::get_transfer_complete_flag() {
- shared
- .rx_transfer
- .lock(|spi_dma| spi_dma.clear_transfer_complete_interrupt());
- let filled_buffer = shared.rx_transfer.lock(|spi_dma| {
- let (result, _) = spi_dma
- .next_transfer(local.rx_buffer.take().unwrap())
- .unwrap();
- result
- });
- match filled_buffer[0] {
- 1 => shared.led.lock(|led| led.set_low()),
- _ => shared.led.lock(|led| led.set_high()),
+ let mut rx_transfer = cx.shared.rx_transfer;
+ let mut led = cx.shared.led;
+ let rx_buffer = cx.local.rx_buffer;
+ rx_transfer.lock(|transfer| {
+ if transfer.is_fifo_error() {
+ transfer.clear_fifo_error();
  }
- *local.rx_buffer = Some(filled_buffer);
- }
+ if transfer.is_transfer_complete() {
+ transfer.clear_transfer_complete();
+
+ let (filled_buffer, _) = transfer.next_transfer(rx_buffer.take().unwrap()).unwrap();
+ match filled_buffer[0] {
+ 1 => led.lock(|led| led.set_low()),
+ _ => led.lock(|led| led.set_high()),
+ }
+ *rx_buffer = Some(filled_buffer);
+ }
+ });
  }
 
  // We either send [1,2,3] or [4,5,6] depending on which buffer was loaded
- #[task(binds = DMA1_STREAM5, shared = [tx_transfer, led], local = [tx_buffer])]
+ #[task(binds = DMA1_STREAM5, shared = [tx_transfer], local = [tx_buffer])]
  fn on_sending(cx: on_sending::Context) {
- let on_sending::Context { mut shared, local } = cx;
- if Stream5::<DMA1>::get_fifo_error_flag() {
- shared
- .tx_transfer
- .lock(|spi_dma| spi_dma.clear_fifo_error_interrupt());
- }
- if Stream5::<DMA1>::get_transfer_complete_flag() {
- shared
- .tx_transfer
- .lock(|spi_dma| spi_dma.clear_transfer_complete_interrupt());
- let filled_buffer = shared.tx_transfer.lock(|spi_dma| {
- let (result, _) = spi_dma
- .next_transfer(local.tx_buffer.take().unwrap())
- .unwrap();
- result
- });
- *local.tx_buffer = Some(filled_buffer);
- }
+ let mut tx_transfer = cx.shared.tx_transfer;
+ let tx_buffer = cx.local.tx_buffer;
+ tx_transfer.lock(|transfer| {
+ if transfer.is_fifo_error() {
+ transfer.clear_fifo_error();
+ }
+ if transfer.is_transfer_complete() {
+ transfer.clear_transfer_complete();
+ let (filled_buffer, _) = transfer.next_transfer(tx_buffer.take().unwrap()).unwrap();
+ *tx_buffer = Some(filled_buffer);
+ }
+ });
  }
 }

examples/spi-dma.rs

@@ -10,7 +10,7 @@ use cortex_m_rt::entry;
 use embedded_hal::spi::{Mode, Phase, Polarity};
 use stm32f4xx_hal::pac::interrupt;
 use stm32f4xx_hal::{
- dma::{config, traits::StreamISR, MemoryToPeripheral, Stream4, StreamsTuple, Transfer},
+ dma::{config, MemoryToPeripheral, Stream4, StreamsTuple, Transfer},
  gpio::Speed,
  pac,
  prelude::*,
@@ -101,11 +101,11 @@ fn DMA2_STREAM4() {
  });
 
  // Its important to clear fifo errors as the transfer is paused until it is cleared
- if Stream4::<pac::DMA1>::get_fifo_error_flag() {
- transfer.clear_fifo_error_interrupt();
+ if transfer.is_fifo_error() {
+ transfer.clear_fifo_error();
  }
- if Stream4::<pac::DMA1>::get_transfer_complete_flag() {
- transfer.clear_transfer_complete_interrupt();
+ if transfer.is_transfer_complete() {
+ transfer.clear_transfer_complete();
  unsafe {
  static mut BUFFER: [u8; ARRAY_SIZE] = [0; ARRAY_SIZE];
  for (i, b) in BUFFER.iter_mut().enumerate() {