Using ARCH_FOO symbol is preferred than SOC_FOO.
Set obj-y for starfive/ in Makefile, so the StarFive drivers
can be compiled with COMPILE_TEST=y but ARCH_STARFIVE=n.

Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

The clock control registers on the StarFive JH7100 and JH7110 work
identically, so factor out the code then drivers for the two SoCs
can share it without depending on each other. No functional change.

Tested-by: Tommaso Merciai <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Rename clk-starfive-jh7100.h to clk-starfive-jh71x0.h for making
the code to be common.

Tested-by: Tommaso Merciai <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Rename some variables from "jh7100" or "JH7100" to "jh71x0"
or "JH71X0".

Tested-by: Tommaso Merciai <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Using ARCH_FOO symbol is preferred than SOC_FOO.

Reviewed-by: Philipp Zabel <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

This moves the StarFive JH7100 reset driver to a new subdirectory in
preparation for adding more StarFive reset drivers.

Reviewed-by: Philipp Zabel <[email protected]>
Tested-by: Tommaso Merciai <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

The StarFive JH7100 SoC has additional reset controllers for audio and
video, but the registers follow the same structure. On the JH7110 the
reset registers don't get their own memory range, but instead follow the
clock control registers. The registers still follow the same structure
though, so let's factor out the common code to handle all these cases.

Tested-by: Tommaso Merciai <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Extract the common JH71X0 reset code for reusing them to
support JH7110 SoC.

Tested-by: Tommaso Merciai <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

For the common code will be shared with the StarFive JH7110 SoC.

Tested-by: Tommaso Merciai <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

We currently use 64bit I/O on the 32bit registers. This works because
there are an even number of assert and status registers, so they're only
ever accessed in pairs on 64bit boundaries.

There are however other reset controllers for audio and video on the
JH7100 SoC with only one status register that isn't 64bit aligned so
64bit I/O results in an unaligned access exception.

Switch to 32bit I/O in preparation for supporting these resets too.

Tested-by: Tommaso Merciai <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Add bindings for the system clock and reset generator (SYSCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.

Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

…erator

Add bindings for the always-on clock and reset generator (AONCRG) on the
JH7110 RISC-V SoC by StarFive Ltd.

Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Add driver for the StarFive JH7110 system clock controller and
register an auxiliary device for system reset controller which
is named as "reset-sys".

Tested-by: Tommaso Merciai <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Co-developed-by: Hal Feng <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Add driver for the StarFive JH7110 always-on clock controller
and register an auxiliary device for always-on reset controller
which is named as "reset-aon".

Tested-by: Tommaso Merciai <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Co-developed-by: Hal Feng <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Add auxiliary driver to support StarFive JH7110 system
and always-on resets.

Tested-by: Tommaso Merciai <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Add compatible string for the StarFive JH7110 clint.

Reviewed-by: Conor Dooley <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Add compatible string for StarFive JH7110 plic.

Reviewed-by: Conor Dooley <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Add a new compatible string in cpu.yaml for SiFive S7 CPU
core which is used on SiFive U74-MC core complex etc.

Reviewed-by: Conor Dooley <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Add initial device tree for the JH7110 RISC-V SoC by StarFive
Technology Ltd.

Tested-by: Tommaso Merciai <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Co-developed-by: Jianlong Huang <[email protected]>
Signed-off-by: Jianlong Huang <[email protected]>
Co-developed-by: Hal Feng <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Add pin function definitions for StarFive JH7110 SoC.

Tested-by: Tommaso Merciai <[email protected]>
Co-developed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Jianlong Huang <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Add a minimal device tree for StarFive JH7110 VisionFive 2 board
which has version A and version B. Support booting and basic
clock/reset/pinctrl/uart drivers.

Tested-by: Tommaso Merciai <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Acked-by: Conor Dooley <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Co-developed-by: Jianlong Huang <[email protected]>
Signed-off-by: Jianlong Huang <[email protected]>
Co-developed-by: Hal Feng <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Add the pmu controller node for the Starfive JH7110 SoC. The PMU needs
to be used by other modules such as VPU, ISP, etc.

Signed-off-by: Walker Chen <[email protected]>

Add documentation to describe StarFive System Controller Registers.

Signed-off-by: William Qiu <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>

Add stg_syscon/sys_syscon/aon_syscon node for JH7110 Soc.

Signed-off-by: William Qiu <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>

…set generator

Add bindings for the System-Top-Group clock and reset generator (STGCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Signed-off-by: Xingyu Wu <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>

Add auxiliary_device_id to support StarFive JH7110 System-Top-Group resets
of which the auxiliary device name is "clk_starfive_jh71x0.reset-stg".

Signed-off-by: Xingyu Wu <[email protected]>

Add driver for the StarFive JH7110 System-Top-Group clock controller.

Signed-off-by: Emil Renner Berthing <[email protected]>
Co-developed-by: Xingyu Wu <[email protected]>
Signed-off-by: Xingyu Wu <[email protected]>

…d reset generator

Add bindings for the Image-Signal-Process clock and reset
generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd.

Signed-off-by: Xingyu Wu <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>

Add auxiliary_device_id to support StarFive JH7110 Image-Signal-Process
resets of which the auxiliary device name is
"clk_starfive_jh71x0.reset-isp".

Signed-off-by: Xingyu Wu <[email protected]>

Add driver for the StarFive JH7110 Image-Signal-Process clock controller.

Signed-off-by: Xingyu Wu <[email protected]>

…generator

Add bindings for the Video-Output clock and reset generator (VOUTCRG)
on the JH7110 RISC-V SoC by StarFive Ltd.

Signed-off-by: Xingyu Wu <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>

Add auxiliary_device_id to support StarFive JH7110 Video-Output resets
of which the auxiliary device name is "clk_starfive_jh71x0.reset-vout".

Signed-off-by: Xingyu Wu <[email protected]>

Add driver for the StarFive JH7110 Video-Output clock controller.

Signed-off-by: Xingyu Wu <[email protected]>

Add DVP and HDMI TX pixel external fixed clocks and the rates are
74.25MHz and 297MHz.

Signed-off-by: Xingyu Wu <[email protected]>

Add STGCRG/ISPCRG/VOUTCRG new node to support JH7110
System-Top-Group, Image-Signal-Process and Video-Output
clock and reset drivers for the JH7110 RISC-V SoC.

Signed-off-by: Xingyu Wu <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>

Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.

Signed-off-by: Xingyu Wu <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>

Add driver for the StarFive JH7110 PLL clock controller.

Signed-off-by: Xingyu Wu <[email protected]>

Add optional compatible and patternProperties.

Signed-off-by: Xingyu Wu <[email protected]>

Add PLL clock inputs from PLL clock generator.

Signed-off-by: Xingyu Wu <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>

Modify PLL clocks source to be got from dts instead of
the fixed factor clocks.

Signed-off-by: Xingyu Wu <[email protected]>

Add the PLL clock node for the Starfive JH7110 SoC and
modify the SYSCRG node to add PLL clocks.

Signed-off-by: Xingyu Wu <[email protected]>

Add bindings to describe the watchdog for the StarFive JH7100/JH7110 SoC.
And Use JH7100 as first StarFive SoC with watchdog.

Signed-off-by: Xingyu Wu <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>

Add watchdog driver for the StarFive JH7100 and JH7110 SoC.

Signed-off-by: Xingyu Wu <[email protected]>

Add watchdog node for the StarFive JH7100 RISC-V SoC.

Signed-off-by: Xingyu Wu <[email protected]>
Reviewed-by: Emil Renner Berthing <[email protected]>

Add the watchdog node for the Starfive JH7110 SoC.

Signed-off-by: Xingyu Wu <[email protected]>

Add bindings for the timer on the JH7110 RISC-V SoC
by StarFive Technology Ltd.

Signed-off-by: Xingyu Wu <[email protected]>

Add timer driver for the StarFive JH7110 SoC.

Signed-off-by: Xingyu Wu <[email protected]>

Add the timer node for the Starfive JH7110 SoC.

Signed-off-by: Xingyu Wu <[email protected]>

Adds the mmc node for the StarFive JH7110 SoC.
Set mmco node to emmc and set mmc1 node to sd.

Signed-off-by: William Qiu <[email protected]>

The QSPI controller needs three reset items to work properly on JH7110 SoC,
so there is need to change the maxItems's value to 3 and add minItems
whose value is equal to 2. Other platforms do not have this constraint.

Signed-off-by: William Qiu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

Add QSPI reset operation in device probe and add RISCV support to
QUAD SPI Kconfig.

Co-developed-by: Ziv Xu <[email protected]>
Signed-off-by: Ziv Xu <[email protected]>
Signed-off-by: William Qiu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>

Add the quad spi controller node for the Starfive JH7110 SoC.

Signed-off-by: William Qiu <[email protected]>

Add documentation to describe StarFive Pulse Width Modulation
controller driver.

Signed-off-by: William Qiu <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>

Add Pulse Width Modulation driver support for StarFive
JH7110 soc.

Signed-off-by: Hal Feng <[email protected]>
Signed-off-by: William Qiu <[email protected]>

Adding StarFive PWM controller node to VisionFive 2 SoC.

Signed-off-by: William Qiu <[email protected]>

Add dwmac-5.20 IP version to snps.dwmac.yaml

Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Samin Guo <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Tested-by: Tommaso Merciai <[email protected]>

Add "snps,dwmac-5.20" compatible string for 5.20 version that can avoid
to define some platform data in the glue layer.

Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Samin Guo <[email protected]>
Tested-by: Tommaso Merciai <[email protected]>

According to:
stmmac_platform.c: stmmac_probe_config_dt
stmmac_main.c: stmmac_dvr_probe

dwmac controller may require one (stmmaceth) or two (stmmaceth+ahb)
reset signals, and the maxItems of resets/reset-names is going to be 2.

The gmac of Starfive Jh7110 SOC must have two resets.
it uses snps,dwmac-5.20 IP.

Signed-off-by: Samin Guo <[email protected]>
Tested-by: Tommaso Merciai <[email protected]>

Add documentation to describe StarFive dwmac driver(GMAC).

Signed-off-by: Yanhong Wang <[email protected]>
Signed-off-by: Samin Guo <[email protected]>
Tested-by: Tommaso Merciai <[email protected]>

This adds StarFive dwmac driver support on the StarFive JH7110 SoC.

Co-developed-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Samin Guo <[email protected]>
Tested-by: Tommaso Merciai <[email protected]>

dwmac supports multiple modess. When working under rmii and rgmii,
you need to set different phy interfaces.

According to the dwmac document, when working in rmii, it needs to be
set to 0x4, and rgmii needs to be set to 0x1.

The phy interface needs to be set in syscon, the format is as follows:
starfive,syscon: <&syscon, offset, shift>

Signed-off-by: Samin Guo <[email protected]>
Tested-by: Tommaso Merciai <[email protected]>

Add JH7110 ethernet device node to support gmac driver for the JH7110
RISC-V SoC.

Signed-off-by: Yanhong Wang <[email protected]>
Signed-off-by: Samin Guo <[email protected]>
Tested-by: Tommaso Merciai <[email protected]>

v1.3B:
  v1.3B uses motorcomm YT8531(rgmii-id phy) x2, need delay and
  inverse configurations.
  The tx_clk of v1.3B uses an external clock and needs to be
  switched to an external clock source.

v1.2A:
  v1.2A gmac0 uses motorcomm YT8531(rgmii-id) PHY, and needs delay
  configurations.
  v1.2A gmac1 uses motorcomm YT8512(rmii) PHY, and needs to
  switch rx and rx to external clock sources.

Signed-off-by: Samin Guo <[email protected]>
Tested-by: Tommaso Merciai <[email protected]>

Add bindings for the temperature sensor on the StarFive JH7100 and
JH7110 SoCs.

Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>
Reviewed-by: Rob Herring <[email protected]>

Add driver for the StarFive JH71x0 temperature sensor. You
can enable/disable it and read temperature in milli Celcius
through sysfs.

Signed-off-by: Emil Renner Berthing <[email protected]>
Co-developed-by: Samin Guo <[email protected]>
Signed-off-by: Samin Guo <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Add temperature sensor support for StarFive JH7110 SoC.

Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

Add thermal-zones for StarFive VisionFive 2 board.

Signed-off-by: Emil Renner Berthing <[email protected]>
Signed-off-by: Hal Feng <[email protected]>

… JH7110 dma

The DMA controller needs two reset items to work properly on JH7110 SoC,
so there is need to constrain the items' value to 2, other platforms
have 1 reset item at most.

Signed-off-by: Walker Chen <[email protected]>
Reviewed-by: Rob Herring <[email protected]>

Add DMA reset operation in device probe and use different configuration
on CH_CFG registers according to match data. Update all uses of
of_device_is_compatible with of_device_get_match_data.

Signed-off-by: Walker Chen <[email protected]>

Add the dma controller node for the Starfive JH7110 SoC.

Signed-off-by: Walker Chen <[email protected]>

Adding StarFive TRNG controller node to VisionFive 2 board.

Co-developed-by: Jenny Zhang <[email protected]>
Signed-off-by: Jenny Zhang <[email protected]>
Signed-off-by: Jia Jie Ho <[email protected]>

Add documentation to describe StarFive cryptographic engine.

Co-developed-by: Huan Feng <[email protected]>
Signed-off-by: Huan Feng <[email protected]>
Signed-off-by: Jia Jie Ho <[email protected]>
Reviewed-by: Rob Herring <[email protected]>

Adding device probe and DMA init for StarFive cryptographic module.

Co-developed-by: Huan Feng <[email protected]>
Signed-off-by: Huan Feng <[email protected]>
Signed-off-by: Jia Jie Ho <[email protected]>

Add StarFive cryptographic module and dedicated DMA controller node to
VisionFive 2 SoCs.

Co-developed-by: Huan Feng <[email protected]>
Signed-off-by: Huan Feng <[email protected]>
Signed-off-by: Jia Jie Ho <[email protected]>
Acked-by: Palmer Dabbelt <[email protected]>

Adding hash/HMAC support for SHA-2 and SM3 to StarFive cryptographic
module.

Co-developed-by: Huan Feng <[email protected]>
Signed-off-by: Huan Feng <[email protected]>
Signed-off-by: Jia Jie Ho <[email protected]>

StarFive SoCs like the jh7110 use a MIPI D-PHY RX controller based on
a M31 IP. Add a binding for it.

Signed-off-by: Changhuang Liang <[email protected]>

Add mipi dphy rx support for the StarFive JH7110 SoC. It is used to
transfer CSI camera data.

Signed-off-by: Changhuang Liang <[email protected]>

Add dphy rx node for the StarFive JH7110 SoC. It is used to transfer CSI
camera data.

Signed-off-by: Changhuang Liang <[email protected]>

Add the bindings documentation for Starfive JH7110 Camera Subsystem
which is used for handing image sensor data.

Signed-off-by: Jack Zhu <[email protected]>

Convert DT bindings document for Cadence MIPI-CSI2 RX controller
to DT schema format and add new properties.

Signed-off-by: Jack Zhu <[email protected]>

Add the file 'starfive_camss.rst' that documents the Starfive Camera
Subsystem driver which is used for handing image sensor data.

Signed-off-by: Jack Zhu <[email protected]>

Add support for external MIPI D-PHY and Starfive JH7110 SoC which
has the cadence csi2 receiver.

Signed-off-by: Jack Zhu <[email protected]>

Add an entry for Starfive Camera Subsystem driver.

Signed-off-by: Jack Zhu <[email protected]>

Add the driver for Starfive Camera Subsystem found on
Starfive JH7110 SoC. It is used for handing image sensor
data.

Signed-off-by: Jack Zhu <[email protected]>

Add StarFive JH7110 SoC USB 2.0/3.0 and PCIe 2.0 PHY dt-binding.
PCIe 2.0 phy can use as USB 3.0 PHY.

Signed-off-by: Minda Chen <[email protected]>

Add Starfive JH7110 SoC PCIe 2.0 and USB 2.0 PHY driver support.
PCIe 2.0 PHY can used as USB 3.0 PHY

Signed-off-by: Minda Chen <[email protected]>

The dt-binding doc of Cadence USBSS-DRD controller wrapper
layer.

Signed-off-by: Minda Chen <[email protected]>
Reviewed-by: Peter Chen <[email protected]>

There is a Cadence USB3 core for JH7110 SoCs, the cdns
core is the child of this USB wrapper module device.

Signed-off-by: Minda Chen <[email protected]>

USB Glue layer and Cadence USB subnode configuration,
also includes USB and PCIe phy dts configuration.

Signed-off-by: Minda Chen <[email protected]>

…unction

Currently suspend_save_csrs() and suspend_restore_csrs() functions are
statically defined in the suspend.c. Change the function's attribute
to public so that the functions can be used by hibernation as well.

Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
Reviewed-by: Mason Huo <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>

The cpu_resume() function is very similar for the suspend to disk and
suspend to ram cases. Factor out the common code into suspend_restore_csrs
macro and suspend_restore_regs macro.

Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>

Currently kernel_page_present() function doesn't support huge page
detection causes the function to mistakenly return false to the
hibernation core.

Add huge page detection to the function to solve the problem.

Fixes: 9e953cd ("riscv: Introduce huge page support for 32/64bit kernel")
Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
Reviewed-by: Mason Huo <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Alexandre Ghiti <[email protected]>

Low level Arch functions were created to support hibernation.
swsusp_arch_suspend() relies code from __cpu_suspend_enter() to write
cpu state onto the stack, then calling swsusp_save() to save the memory
image.

Arch specific hibernation header is implemented and is utilized by the
arch_hibernation_header_restore() and arch_hibernation_header_save()
functions. The arch specific hibernation header consists of satp, hartid,
and the cpu_resume address. The kernel built version is also need to be
saved into the hibernation image header to making sure only the same
kernel is restore when resume.

swsusp_arch_resume() creates a temporary page table that covering only
the linear map. It copies the restore code to a 'safe' page, then start
to restore the memory image. Once completed, it restores the original
kernel's page table. It then calls into __hibernate_cpu_resume()
to restore the CPU context. Finally, it follows the normal hibernation
path back to the hibernation core.

To enable hibernation/suspend to disk into RISCV, the below config
need to be enabled:
- CONFIG_ARCH_HIBERNATION_HEADER
- CONFIG_ARCH_HIBERNATION_POSSIBLE

Signed-off-by: Sia Jee Heng <[email protected]>
Reviewed-by: Ley Foon Tan <[email protected]>
Reviewed-by: Mason Huo <[email protected]>
Reviewed-by: Conor Dooley <[email protected]>