Use `riscv` section for RISC-V targets #856

romancardenas · 2024-07-01T07:22:09Z

This PR uses my proposed riscv SVD section to generate RISC-V PACs using the new set of traits in riscv-pac.

In this PR, the mod interrupt in RISC-V targets is handled differently, and includes:

ExternalInterrupts (very similar to current Interrupts)
CoreInterrupts (this is new, previously it just assumed the peripheral follows the RISC-V standard)
Priority levels (necessary for interfacing standard peripherals with trait bounds)
HartIds (necessary for interfacing standard peripherals with trait bounds).

Also, the PAC does not directly generate all the handlers array and so on. Instead, it relies on macros exposed in riscv-pac.

I still need some time to pollish everything, but feedback is more than welcome :)

Solves #786

romancardenas · 2024-07-01T07:35:45Z

This PR shows how an updated PAC would look like over e310x chips

romancardenas · 2024-07-03T14:41:32Z

Added the unstable-riscv feature to optionally activate the proposed new functionality. I still have to include support for riscv-peripheral implementations depending on the name of the peripheral.

Emilgardis

good start! should probably be marked as a draft, I see a bunch of todos

CHANGELOG.md

romancardenas · 2024-08-20T15:38:00Z

Yes! I'm currently working on a bunch of changes to use standard peripherals when possible, so it will take a few more iterations until it is ready to merge

romancardenas · 2024-08-20T16:42:03Z

As shown in this PR, now it is possible to use riscv-peripheral standard implementations (i.e., CLINT and PLIC) instead of the ones generated by svd2rust. This shows the new outcome. Note that it only takes one macro call per standard peripheral:

riscv_peripheral :: clint_codegen ! (base 0x2000000 , mtimecmps [mtimecmp0 = (crate :: interrupt :: Hart :: H0 , "[0](crate::interrupt::Hart::H0)")] , msips [msip0 = (crate :: interrupt :: Hart :: H0 , "[0](crate::interrupt::Hart::H0)")] ,);
riscv_peripheral :: plic_codegen ! (base 0xC000000 , ctxs [ctx0 = (crate :: interrupt :: Hart :: H0 , "[0](crate::interrupt::Hart::H0)")] ,);

To do list

Configuration parameter to select whether to use the standard macros or the old-school way.
A mechanism to specify the CLINT's clock frequency to benefit from its embedded-hal implementation.
Configuration parameter to activate the use of async_delay flag for CLINT.

Regarding the second point: what do you think about providing the CLINT clock frequency via a configuration parameter?

romancardenas · 2024-08-22T15:16:00Z

I started with the configuration parameters... and decided to explore using configuration parameters only, leaving the SVD file untouched.

For the E310x chip, the configuration file would look like this.
What do you think about this alternative? I personally like it more.

burrbull · 2024-08-28T04:01:55Z

I started with the configuration parameters... and decided to explore using configuration parameters only, leaving the SVD file untouched.

For the E310x chip, the configuration file would look like this.
What do you think about this alternative? I personally like it more.

Makes sense. But why a TOML? YAML should looks much cleaner for such things.

Also what should we do with svd-rs changes and released crates?

romancardenas · 2024-08-28T07:04:12Z

Makes sense. But why a TOML? YAML should looks much cleaner for such things.

I converted the TOML file to YAML and the following command fails:

svd2rust --target riscv -c svd2rust.yaml -g -i e310x.svd
[ERROR svd2rust] Failed to parse value for parser #2
    
    Caused by:
        0: Failed parse TOML
        1: TOML parse error at line 1, column 16
             |
           1 | core_interrupts:
             |                ^
           expected `.`, `=`

From here, it looks like svd2rust only supports TOML configuration files

Also what should we do with svd-rs changes and released crates?

If we prefer this isolated configuration file approach (which I do), then all the stuff under the unstable-riscv feature will no longer be necessary, as all the RISC-V magic will happen in svd2rust only.

burrbull · 2024-08-28T07:55:13Z

I think this should not be in svd2rust config file. It's better to use another --riscv-config file.yaml option as you may want to use different configs for different input SVDs but with the same svd2rust.toml.

romancardenas · 2024-08-29T17:06:17Z

I addressed your suggestions. I'm not sure if my independent YAML file implementation is the best approach, let me know what you think.

You can see how I use it for E310x chips here

romancardenas · 2024-09-04T13:44:48Z

PAC using this PR: e310x
HAL using the result PAC: e310x-hal
BSP using the resulting HAL: hifive1
- It contains an example using the PLIC and CLINT peripherals. You can emulate the CLINT example with QEMU
Software Interrupt handler SLIC: riscv-slic

burrbull · 2024-09-25T12:11:39Z

@romancardenas still a draft?

romancardenas · 2024-09-25T13:04:09Z

Not really, I don't expect to add any changes. I'm waiting to release the next version of the riscv crates in crates.io, though.

burrbull · 2024-09-25T13:21:10Z

src/config.rs

+ pub core_interrupts: Option<Vec<RiscvEnumItem>>,
+ pub exceptions: Option<Vec<RiscvEnumItem>>,
+ pub priorities: Option<Vec<RiscvEnumItem>>,
+ pub harts: Option<Vec<RiscvEnumItem>>,


Is None different from Some(Vec::empty) here?

Currently, if you define core_interrupts in your YAML file, svd2rust will generate a custom CoreInterrupt struct for your target, regardless of whether it is empty or not. Thus, an empty vector would probably be meaningless. I can change this behavior following any of your design decisions.

I want to say that you can leave just Vec<T> and check vec.is_empty() instead of option.is_some.

Possibly you should also mark a field with serde(default). Not sure.

Will take a look to your suggestion!

burrbull · 2024-10-21T05:42:12Z

I think this should not be in svd2rust config file. It's better to use another --riscv-config file.yaml option as you may want to use different configs for different input SVDs but with the same svd2rust.toml.

What about this?

I'd want to see something like this:

/// Common svd2rust options
struct Config {
   ...
   /// Path to YAML file with chip related settings
   pub settings: Option<PathBuf>,
}

#[non_exhaustive]
struct Settings {
    pub riscv_config: Option<RiscvConfig>,
    
    // other settings (for example #576)
}

romancardenas · 2024-10-21T06:49:44Z

I'd want to see something like this:

/// Common svd2rust options
struct Config {
   ...
   /// Path to YAML file with chip related settings
   pub settings: Option<PathBuf>,
}

#[non_exhaustive]
struct Settings {
    pub riscv_config: Option<RiscvConfig>,
    
    // other settings (for example #576)
}

Oh, I see! I added a riscv_config parameter to the general configuration, but maybe it will be more scalable having a separate settings.yml file that includes the RISC-V-specific configuration (together with potentially new parameters such as Zaamo-only registers).

romancardenas · 2024-10-21T12:08:56Z

@burrbull Let me know if the new version looks as you expected

burrbull · 2024-10-21T12:44:36Z

src/generate/device.rs

@@ -30,6 +30,14 @@ pub fn render(d: &Device, config: &Config, device_x: &mut String) -> Result<Toke
 }
 };

+ let _settings = match config.settings.as_ref() {


Why is it underscored?

burrbull · 2024-10-21T12:45:25Z

Cargo.toml

@@ -35,13 +35,14 @@ default = ["bin", "json", "yaml"]
 bin = ["dep:clap", "dep:env_logger", "serde", "dep:irx-config"]
 json = ["dep:serde_json"]
 yaml = ["dep:serde_yaml"]
-unstable-riscv = ["irx-config/yaml"]
+unstable-riscv = []


Is it unstable yet?

burrbull · 2024-10-21T12:50:13Z

Squash commits, please.

romancardenas · 2024-10-21T15:06:52Z

Done

We use setting.yaml to support riscv 0.12.0 and riscv-rt 0.13.0 This feature also allows RISC-V targets to use standard peripheral implementations with the riscv-peripheral crate.

burrbull · 2024-10-21T16:12:04Z

Please, revert commits from svd-rs.

romancardenas requested a review from a team as a code owner July 1, 2024 07:22

romancardenas mentioned this pull request Aug 20, 2024

Support for non-standard exception and interrupts (clean) rust-embedded/riscv#223

Merged

Emilgardis reviewed Aug 20, 2024

View reviewed changes

CHANGELOG.md Outdated Show resolved Hide resolved

Emilgardis marked this pull request as draft August 20, 2024 15:36

Emilgardis requested review from Emilgardis and a team August 20, 2024 15:36

burrbull reviewed Sep 25, 2024

View reviewed changes

romancardenas force-pushed the master branch from 731e1fe to b198aec Compare October 20, 2024 08:34

romancardenas marked this pull request as ready for review October 20, 2024 08:36

burrbull mentioned this pull request Oct 21, 2024

Add support for atomic xor/clear/set register operations for Raspberry Pi RP2040 microcontroller #535

Open

burrbull reviewed Oct 21, 2024

View reviewed changes

romancardenas force-pushed the master branch from f598498 to c9979d9 Compare October 21, 2024 15:05

settings.yaml file for target-specific configurations.

90ef2a6

We use setting.yaml to support riscv 0.12.0 and riscv-rt 0.13.0 This feature also allows RISC-V targets to use standard peripheral implementations with the riscv-peripheral crate.

romancardenas force-pushed the master branch from c9979d9 to 90ef2a6 Compare October 21, 2024 15:10

Update riscv CI to 0.12.1

7468bd6

burrbull approved these changes Oct 21, 2024

View reviewed changes

burrbull added this pull request to the merge queue Oct 21, 2024

Merged via the queue into rust-embedded:master with commit 8b809ac Oct 21, 2024
46 checks passed

This was referenced Oct 21, 2024

Revert riscv elements and unstable-riscv feature rust-embedded/svd#276

Merged

Update crates to work with riscv 0.12 and riscv-rt 0.13 riscv-rust/e310x#38

Open

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Use `riscv` section for RISC-V targets #856

Use `riscv` section for RISC-V targets #856

romancardenas commented Jul 1, 2024

romancardenas commented Jul 1, 2024

romancardenas commented Jul 3, 2024

Emilgardis left a comment

romancardenas commented Aug 20, 2024

romancardenas commented Aug 20, 2024 •

edited

Loading

romancardenas commented Aug 22, 2024

burrbull commented Aug 28, 2024

romancardenas commented Aug 28, 2024

burrbull commented Aug 28, 2024

romancardenas commented Aug 29, 2024

romancardenas commented Sep 4, 2024 •

edited

Loading

burrbull commented Sep 25, 2024

romancardenas commented Sep 25, 2024

burrbull Sep 25, 2024

romancardenas Sep 25, 2024

burrbull Oct 20, 2024

romancardenas Oct 20, 2024

burrbull commented Oct 21, 2024

romancardenas commented Oct 21, 2024

romancardenas commented Oct 21, 2024

burrbull Oct 21, 2024

burrbull Oct 21, 2024

burrbull commented Oct 21, 2024

romancardenas commented Oct 21, 2024

burrbull commented Oct 21, 2024

Use riscv section for RISC-V targets #856

Use riscv section for RISC-V targets #856

Conversation

romancardenas commented Jul 1, 2024

romancardenas commented Jul 1, 2024

romancardenas commented Jul 3, 2024

Emilgardis left a comment

Choose a reason for hiding this comment

romancardenas commented Aug 20, 2024

romancardenas commented Aug 20, 2024 • edited Loading

To do list

romancardenas commented Aug 22, 2024

burrbull commented Aug 28, 2024

romancardenas commented Aug 28, 2024

burrbull commented Aug 28, 2024

romancardenas commented Aug 29, 2024

romancardenas commented Sep 4, 2024 • edited Loading

burrbull commented Sep 25, 2024

romancardenas commented Sep 25, 2024

burrbull Sep 25, 2024

Choose a reason for hiding this comment

romancardenas Sep 25, 2024

Choose a reason for hiding this comment

burrbull Oct 20, 2024

Choose a reason for hiding this comment

romancardenas Oct 20, 2024

Choose a reason for hiding this comment

burrbull commented Oct 21, 2024

romancardenas commented Oct 21, 2024

romancardenas commented Oct 21, 2024

burrbull Oct 21, 2024

Choose a reason for hiding this comment

burrbull Oct 21, 2024

Choose a reason for hiding this comment

burrbull commented Oct 21, 2024

romancardenas commented Oct 21, 2024

burrbull commented Oct 21, 2024

Use `riscv` section for RISC-V targets #856

Use `riscv` section for RISC-V targets #856

romancardenas commented Aug 20, 2024 •

edited

Loading

romancardenas commented Sep 4, 2024 •

edited

Loading