RISC-V: adoption of riscv-pac

[romancardenas]

The @rust-embedded/risc-v team is preparing a few changes for the RISC-V ecosystems.
One of these changes is the riscv-pac crate, which will hold all the interrupt-related traits any RISC-V PAC should implement.

I don't know currently how to integrate this in svd2rust, but I would be happy to help :)

[romancardenas]

We are trying to make the riscv ecosystem more flexible by allowing custom, non-standard interrupt sources in this PR. There is still some work to be done, but I would like to elaborate on our new approach and how this affects svd2rust.

The riscv-pac crate and interrupt types

The riscv-pac crate defines two types of interrupt sources:

• CoreInterruptNumber: interrupt sources that has a core interrupt number associated to them (e.g., MachineExternal in the RISC-V standard).
• ExternalInterruptNumber: interrupt sources assigned to external stimuli (e.g., GPIOs) that are not handled by the core directly. Instead, the core interacts with an external interrupt peripheral (e.g., PLIC) to deal with them. This peripheral can be seen as a demultiplexer that triggers a single core interrupt that is shared among all the external interrupt sources.

The riscv-pac crate provides a set of macros to ease the implementation of these traits. The idea is that svd2rust can use these macros to automatize trait implementations.

We need special code for core interrupts

So, core interrupts need additional code that currently is not supported by svd2rust. Namely, we need to:

1. Define the enum with all the core interrupt handlers (something like this in riscv-rt).
2. Define the __CORE_INTERRUPTS static array.
3. Define the _dispatch_core_interrupt function, which is required by riscv-rt to deal with core interrupts.
4. For vectored mode, we need also to provide the vector table.
5. For vectored mode, we also need to add the _start_Interrupt_handler symbols to the linker script

We need a new convention for feature gates of the new code

All the code generation will be automatically done by helper macros provided by the riscv-pac. However, we need to get into an agreement for feature gates (e.g., rt and v-trap) similar to what is currently going on with __EXTERNAL_INTERRUPTS.

We need a way to define core interrupts in the SVD file

I propose adding a new interrupts tag at the same level as peripherals:

<device>
  ...
  <interrupts> <!-- Section with all core interrupt sources -->
    ...
    <interrupt>
      <name>MachineExternal</name>
      <value>11</value>
    </interrupt>
  </interrupts>
  <peripherals>
    ...                  <!-- External interrupt sources are defined in each peripheral -->
  </peripherals>
</device>