[monotonics] Fix STM32 read-modify-write race condition

rtic-monotonics/CHANGELOG.md

@@ -15,6 +15,10 @@ For each category, *Added*, *Changed*, *Fixed* add new entries at the top!
 
 - Update `esp32c3` dependency
 
+### Fixed
+
+- Race condition that caused missed interrupts on STM32 timers
+
 ## v2.0.2 - 2024-07-05
 
 ### Added

rtic-monotonics/src/stm32.rs

@@ -248,7 +248,10 @@ macro_rules! make_timer {
 
  // The above line raises an update event which will indicate that the timer is already finished.
  // Since this is not the case, it should be cleared.
- $timer.sr().modify(|r| r.set_uif(false));
+ $timer.sr().write(|r| {
+ r.0 = !0;
+ r.set_uif(false);
+ });
 
  $tq.initialize(Self {});
  $overflow.store(0, Ordering::SeqCst);
@@ -294,7 +297,10 @@ macro_rules! make_timer {
  }
 
  fn clear_compare_flag() {
- $timer.sr().modify(|r| r.set_ccif(1, false));
+ $timer.sr().write(|r| {
+ r.0 = !0;
+ r.set_ccif(1, false);
+ });
  }
 
  fn pend_interrupt() {
@@ -312,13 +318,19 @@ macro_rules! make_timer {
  fn on_interrupt() {
  // Full period
  if $timer.sr().read().uif() {
- $timer.sr().modify(|r| r.set_uif(false));
+ $timer.sr().write(|r| {
+ r.0 = !0;
+ r.set_uif(false);
+ });
  let prev = $overflow.fetch_add(1, Ordering::Relaxed);
  assert!(prev % 2 == 1, "Monotonic must have missed an interrupt!");
  }
  // Half period
  if $timer.sr().read().ccif(0) {
- $timer.sr().modify(|r| r.set_ccif(0, false));
+ $timer.sr().write(|r| {
+ r.0 = !0;
+ r.set_ccif(0, false);
+ });
  let prev = $overflow.fetch_add(1, Ordering::Relaxed);
  assert!(prev % 2 == 0, "Monotonic must have missed an interrupt!");
  }