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Clash ethernet core

This project is a fully functional (hopefully) MII ethernet core that can respond to pings

Tiny Tapeout Verilog Project Template

What is Tiny Tapeout?

Tiny Tapeout is an educational project that aims to make it easier and cheaper than ever to get your digital and analog designs manufactured on a real chip.

To learn more and get started, visit https://tinytapeout.com.

Set up your Verilog project

  1. Add your Verilog files to the src folder.
  2. Edit the info.yaml and update information about your project, paying special attention to the source_files and top_module properties. If you are upgrading an existing Tiny Tapeout project, check out our online info.yaml migration tool.
  3. Edit docs/info.md and add a description of your project.
  4. Adapt the testbench to your design. See test/README.md for more information.

The GitHub action will automatically build the ASIC files using OpenLane.

Enable GitHub actions to build the results page

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What next?

More documentation to come...

What is Tiny Tapeout?

TinyTapeout is an educational project that aims to make it easier and cheaper than ever to get your digital designs manufactured on a real chip.

To learn more and get started, visit https://tinytapeout.com.

Building the project locally

  1. Install OpenLane 2 with nix. Set the OPENLANE2_ROOT environment variable to the path where you cloned the openlane2 repository.
  2. Clone tt-support-tools: git clone -b tt06 https://github.com/TinyTapeout/tt-support-tools tt
  3. Run the following command:
rm -rf runs && nix-shell ${OPENLANE2_ROOT}/shell.nix --run "python build.py"

The build.py script will create a runs directory and run the OpenLane flow. The results will be in the runs/wokwi directory.

When you run the build for the first time, nix will download all the dependencies. This can take a while, especially if you haven't configured nix to use binary caches. Once the dependencies are downloaded, the build should take up to ten minutes.

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