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Improved bcm2836/7 IRQ handling #6359

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@P33M P33M commented Sep 13, 2024

First phase of preparing to add platform FIQ support for armv8. Catch some low-hanging fruit first.

Posting as a PR to get autobuilds for all affected platforms (Pi 0 through 3). Only merge if you're feeling brave...

Interrupts are dispatched round-robin but doing so trampled FIQ routing.
Taking a FIQ on a core without a handler installed is fatal.

Only modify bits 1:0 which are the IRQ route bits.

Signed-off-by: Jonathan Bell <[email protected]>
BCM2836 with Cortex-A7 cores has almost the same ARM_LOCAL interrupt
routing logic as BCM2837, so relax the compile guard to CONFIG_SMP not
CONFIG_ARM64.

Signed-off-by: Jonathan Bell <[email protected]>
Also declare as static inline, as they should be.

Signed-off-by: Jonathan Bell <[email protected]>
The ARM64 architecture uses qspinlock which has a fast and slow path.
This isn't ideal for all claimers of a lock operating in interrupt
context. Add a ticket-based lock similar to the armv6/7 implementation.

Based on an upstream patch that was abandoned in favour of qspinlock.

Link: https://patchwork.kernel.org/project/linux-arm-kernel/patch/[email protected]/

Signed-off-by: Jonathan Bell <[email protected]>
Warning on normal behaviour isn't sensible and is spammy. Demote to info.

Signed-off-by: Jonathan Bell <[email protected]>
The local spinlock protects the handlers from racing against each other
on separate cores, hard IRQs don't preempt each other, and
disabling/enabling the interrupt is more expensive than letting the fake
FIQ contend the spinlock.

So turn local_fiq_en/disable into no-ops.

Signed-off-by: Jonathan Bell <[email protected]>
@satmandu
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This is exciting! I imagine this might help with the WARN::dwc_otg_hcd_urb_dequeue:639: Timed out waiting for FSM NP transfer to complete on 2 errors I am getting on a 3b+ running the 64-bit bookworm with a usb device attached?

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P33M commented Sep 13, 2024

At this stage it's more likely to just permute the set of errors you get. There's no guaranteed maximum interrupt latency with this patch series.

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