TEST: Perf branch stack sampling #6330

11cf37e switched to using drm_fb_dma_get_gem_addr instead of drm_fb_dma_get_gem_obj and adding fb->offset[]. However the tiled formats need to compute the offset in a more involved manner than drm_fb_dma_get_gem_addr applies, and we were ending up with the offset for src_[xy] being applied twice. Switch back to using drm_fb_dma_get_gem_obj and fully computing the offsets ourselves. Fixes: 11cf37e ("drm/vc4: Move the buffer offset out of the vc4_plane_state") Signed-off-by: Dave Stevenson <[email protected]>

Add a flag custom_fb_num to denote that the client has requested a specific fbdev node number via node. Signed-off-by: Dave Stevenson <[email protected]>

For situations where there are multiple DRM cards in a system, add a query of DT for "drm_fb" designations for cards to set their preferred /dev/fbN designation. Signed-off-by: Dave Stevenson <[email protected]> drm/fb_helper: Change query for FB designation from drm_fb to drm-fb Fixes: 1216ea5 ("drm/fb-helper: Look up preferred fbdev node number from DT") Signed-off-by: Dave Stevenson <[email protected]>

Apparently aliases are only allowed lower case and hyphens, so swap the use of underscore to hyphen. Fixes: 3aa1f24 ("drm: Look for an alias for the displays to use as the DRM device name") Signed-off-by: Dave Stevenson <[email protected]>

This property can be used to delay deassertion of external fundamental reset, which may be useful for endpoints that require an extended time for internal setup to complete. Signed-off-by: Jonathan Bell <[email protected]>

When factoring out __vc4_hvs_stop_channel, the logic got inverted from if (condition) // stop channel to if (condition) goto out //stop channel out: and also changed the exact register writes used to stop the channel. Correct the logic so that the channel is actually stopped, and revert to the original register writes. Fixes: 6d01a10 ("drm/vc4: crtc: Move HVS init and close to a function") Signed-off-by: Dave Stevenson <[email protected]>

The reset condition for the EMPTY flag in DISPSTATx is 0, so seeing as we've just reset the pipeline there is no guarantee that the flag will denote empty if it hasn't been enabled. Drop the WARN. Signed-off-by: Dave Stevenson <[email protected]>

The code handling freeing stale dlists had 2 issues: - it disabled the interrupt as soon as the first EOF interrupt occurred, even if it didn't clear all stale allocations, thus leading to stale entries - It didn't free stale entries from disabled channels, so eg "kmstest -c 0" could leave a stale alloc on channel 1 floating around. Keep the interrupt enabled whilst there are any outstanding allocs, and discard those on disabled channels. This second channel does require us to call vc4_hvs_stop_channel from vc4_crtc_atomic_disable so that the channel actually gets stopped. Signed-off-by: Dave Stevenson <[email protected]>

Users are reporting running out of DLIST memory. Add a debugfs file to dump out all the allocations. Signed-off-by: Dave Stevenson <[email protected]>

Signed-off-by: Dave Stevenson <[email protected]>

BCM2711 runs pixelvalve at two pixels per clock cycle which results in an unfortunate limitation that odd horizontal timings are not possible. This is apparent on the standard DMT mode of 1366x768@60 which cannot be driven with correct timing. BCM2712 defaults to the same behaviour, but has a mode to support odd timings. While internally it still runs at two pixels per clock, setting the PV_VCONTROL_ODD_TIMING bit makes it appear externally to behave as it is one pixel per clock. Switching to this mode fixes 1366x768@60 mode, and other custom resultions with odd horizontal timings. Signed-off-by: Dom Cobley <[email protected]>

With a DMA FIFO threshold greater than 1 (encoded as 0), it is possible for data in the FIFO to be inaccessible, causing the transfer to fail after a timeout. If the transfer includes a transmission, reduce the RX threshold when the TX completes, otherwise use 1 for the whole transfer (inefficient, but not catastrophic at SPI data rates). See: raspberrypi#5696 Signed-off-by: Phil Elwell <[email protected]>

Certain controllers (dwc-mshc) generate timeout conditions separately to command-completion conditions, where the end result is interrupts are separated in time depending on the current SDCLK frequency. This causes spurious interrupts if SDCLK is slow compared to the CPU's ability to process and return from interrupt. This occurs during card probe with an empty slot where all commands that would generate a response time out. Add a quirk to squelch command response interrupts when a command timeout interrupt is received. Signed-off-by: Jonathan Bell <[email protected]>

The DWC MSHC controller on RP1 needs differentiating from the generic version. Signed-off-by: Jonathan Bell <[email protected]>

Signed-off-by: Nick Bulleid <[email protected]> Added export feature to gpio-poweroff documentation Signed-off-by: Nick Bulleid <[email protected]>

With the new support for a chain of sys_off handlers, gpio-poweroff does not disable a normal shutdown (though it does delay it). There is therefore no need for the noisy WARN from the kernel. Signed-off-by: Phil Elwell <[email protected]>

See: https://forums.raspberrypi.com/viewtopic.php?p=2159344 Signed-off-by: Phil Elwell <[email protected]>

Add the following formats: - V4L2_PIX_FMT_RGB48/V4L2_PIX_FMT_BGR48 48-bit RGB where each colour sample is 16-bits. - V4L2_PIX_FMT_PISP_COMP1_MONO/V4L2_PIX_FMT_PISP_COMP2_MONO 16-bit to 8-bit pisp compressed monochrome pixel format. Signed-off-by: Naushir Patuck <[email protected]>

Users have reported log spam created by "Event Ring Full" xHC event TRBs. These are caused by interrupt latency in conjunction with a very busy set of devices on the bus. The errors are benign, but throughput will suffer as the xHC will pause processing of transfers until the event ring is drained by the kernel. Expand the number of event TRB slots available by increasing the number of event ring segments in the ERST. Controllers have a hardware-defined limit as to the number of ERST entries they can process, so make the actual number in use min(ERST_MAX_SEGS, hw_max). Signed-off-by: Jonathan Bell <[email protected]>

All the handling for the properties was present, but they were never attached to the connector to allow userspace to change them. Add them to the connector. Signed-off-by: Dave Stevenson <[email protected]>

Step wise governor increases the mitigation level when the temperature goes above a threshold and will decrease the mitigation when the temperature falls below the threshold. If it were a case, where the temperature hovers around a threshold, the mitigation will be applied and removed at every iteration. This reaction to the temperature is inefficient for performance. The use of hysteresis temperature could avoid this ping-pong of mitigation by relaxing the mitigation to happen only when the temperature goes below this lower hysteresis value. Signed-off-by: Ram Chandrasekar <[email protected]> Signed-off-by: Lina Iyer <[email protected]> drivers: thermal: step_wise: avoid throttling at hysteresis temperature after dropping below it Signed-off-by: Serge Schneider <[email protected]> Fix hysteresis support in gov_step_wise.c Directly get hyst value instead of going through an optional and, now, unimplemented function. Signed-off-by: Jürgen Kreileder <[email protected]>

The mainline driver has implemented analogue gain using the control V4L2_CID_GAIN instead of V4L2_CID_ANALOGUE_GAIN. libcamera requires V4L2_CID_ANALOGUE_GAIN, and therefore fails. Update the driver to use V4L2_CID_ANALOGUE_GAIN. Signed-off-by: Dave Stevenson <[email protected]>

It is permitted for a plane to be configured such that none of it is on-screen via either negative dest rectangle X,Y offset, or just an offset that is greater than the crtc dimensions. These planes were resized via drm_atomic_helper_check_plane_state such that the source rectangle had a zero width or height, but they still created a dlist entry even though they contributed no pixels. In the case of vc6_plane_mode_set, that it could result in negative values being written into registers, which caused incorrect behaviour. Drop planes that result in a source width or height of 0 pixels to avoid the incorrect rendering. Signed-off-by: Dave Stevenson <[email protected]>

Commit 7cd7065 ("drm/bridge: display-connector: implement bus fmts callbacks") added use of drm_atomic_helper_bridge_* functions, but didn't select the dependency of DRM_KMS_HELPER. If nothing else selected that dependency it resulted in a build failure. Select the missing dependency. Fixes: 7cd7065 ("drm/bridge: display-connector: implement bus fmts callbacks") Signed-off-by: Dave Stevenson <[email protected]>

atomic_check creates a state, and allocates the dlist memory for it such that atomic_flush can not fail. On destroy that dlist allocation was being put in the stale list, even though it had never been programmed into the hardware, therefore doing lots of atomic_checks could consume all the dlist memory and fail. If the dlist has never been programmed into the hardware, then free it immediately. Signed-off-by: Dave Stevenson <[email protected]>

The dmabuf import already checks that the backing buffer is contiguous and rejects it if it isn't. vc4 also requires that the buffer is in the bottom 1GB of RAM, and this is all correctly defined via dma-ranges. However the kernel silently uses swiotlb to bounce dma buffers around if they are in the wrong region. This relies on dma sync functions to be called in order to copy the data to/from the bounce buffer. DRM is based on all memory allocations being coherent with the GPU so that any updates to a framebuffer will be acted on without the need for any additional update. This is fairly fundamentally incompatible with needing to call dma_sync_ to handle the bounce buffer copies, and therefore we have to detect and reject mappings that use bounce buffers. Signed-off-by: Dave Stevenson <[email protected]>

The moplet registers as VC4_ENCODER_TYPE_TXP1 and can be fed from mux output 2 of HVS channel 1. Correct the option which checked for VC4_ENCODER_TYPE_TXP0 Signed-off-by: Dave Stevenson <[email protected]>

MOP uses register offset 0x24 for the high bits of the address, whilst Moplet uses 0x1c. Handle this difference between the block types. Signed-off-by: Dave Stevenson <[email protected]>

Add YAML device tree bindings for the ROHM BU64754 VCM Motor Driver for Camera Autofocus. Signed-off-by: Kieran Bingham <[email protected]> Signed-off-by: Jacopo Mondi <[email protected]>

Add support for the ROHM BU64754 Motor Driver for Camera Autofocus. A V4L2 Subdevice is registered and provides a single V4L2_CID_FOCUS_ABSOLUTE control. Signed-off-by: Kieran Bingham <[email protected]> Signed-off-by: Jacopo Mondi <[email protected]>

Pi 5 uses BL31 as its armstub file, so the reset goes via PSCI. Parse any "reboot" parameter as a partition number to reboot into. N.B. This code path is only used if reboot mode has been set to warm or soft. Signed-off-by: Phil Elwell <[email protected]>

The frame count values moved within registers DISPSTAT1 and DISPSTAT2 with GEN5, so update the accessor function to accommodate that. Fixes: b51cd7a ("drm/vc4: hvs: Fix frame count register readout") Signed-off-by: Dave Stevenson <[email protected]>

Fixes: d869ef6a96a3 ("drm/vc4: Add debugfs node that dumps the vc5 gamma PWL entries") Signed-off-by: Dave Stevenson <[email protected]>

CSI2 devices are meant to use the 1Xnn formats rather than 2Xnn such as MEDIA_BUS_FMT_UYVY8_2X8. For devices with ADV7180_FLAG_MIPI_CSI2 set, use MEDIA_BUS_FMT_UYVY8_1X16. Signed-off-by: Dave Stevenson <[email protected]>

For CSI2 receivers that need to know the link frequency, add it as a control to the driver. Interlaced modes are 216Mbp/s or 108MHz, whilst going through the I2P to deinterlace gives 432Mb/s or 216MHz. Signed-off-by: Dave Stevenson <[email protected]>

The forced conversion of native CS lines into software CS lines is done whether or not the controller has been given any CS lines to use. This breaks the use of the spi0-0cs overlay to prevent SPI from claiming any CS lines, particularly with spidev which doesn't pass in the SPI_NO_CS flag at creation. Use the presence of an empty cs-gpios property as an indication that no CS lines should be used, bypassing the native CS conversion code. See: raspberrypi#5835 Signed-off-by: Phil Elwell <[email protected]>

Signed-off-by: Dom Cobley <[email protected]>

2712D0 has a simpler colourspace conversion matrix block so set that up. Signed-off-by: Dom Cobley <[email protected]>

2712D0 has increased the fifo sizes of MAI_THR blocks, resulting in adjusted bit offsets. Handle that. Signed-off-by: Dom Cobley <[email protected]>

…ve once vc4_hvs_dlist_free_work was iterating through the list of stale dlist entries and reading the frame count and active flags from the hardware for each one. Read the frame count and active flags once, and then use the cached value in the loop. Signed-off-by: Dave Stevenson <[email protected]>

This is largely for debug at present. For reasons unknown we are not getting the end of frame interrupts that should trigger a sweep of stale dlist entries. On allocation failure clear out ALL stale entries, and retry the allocation. Log the interrupt status so we have debug regarding whether the HVS believes the interrupt is enabled. Signed-off-by: Dave Stevenson <[email protected]>

See commit 511ce37 ("mmc: Add MMC host software queue support") Introduced in 5.8, this feature lets the block layer issue up to 2 pending requests to the MMC layer which in certain cases can improve throughput, but in the case of this driver can significantly reduce context switching when performing random reads. On bcm2837 with a performant class A1 card, context switches under FIO random 4k reads go from ~8800 per second to ~5800, with a reduction in hardIRQs per second from ~5800 to ~4000. There is no appreciable difference in throughput. For bcm2835, and for workloads other than random read, HSQ is a wash in terms of throughput and CPU load. So, use it by default. Signed-off-by: Jonathan Bell <[email protected]>

There are three disable bits, one for each bus-instance type. Add a quirk to cover the FS/LS type, and update the slightly mangled quirk descriptions in the process. Signed-off-by: Jonathan Bell <[email protected]>

There are three parkmode disable bits, one for each bus instance type. Add FS/LS and parse the quirk out of DT. Also update the slightly mangled quirk descriptions. Signed-off-by: Jonathan Bell <[email protected]>

With the command line parser now providing the information about the tv mode, use that as the preferred choice for initialising the default of the tv_mode property. Signed-off-by: Dave Stevenson <[email protected]>

Calculate the HCNT and LCNT values for all modes using the rise and fall times of SCL, the aim being a 50/50 mark/space ratio. Signed-off-by: Phil Elwell <[email protected]>

Add support for non-standard bus speeds by treating them as detuned versions of the slowest standard speed not less than the requested speed. Signed-off-by: Phil Elwell <[email protected]>

There are multiple causes of interrupts, errors being one, and only the receipt of data warrants continued polling. See: raspberrypi#2676 Signed-off-by: Phil Elwell <[email protected]>

The dedicated dma40 memcpy code is no longer used, and without a prototype the kernel build fails. Delete it. Signed-off-by: Phil Elwell <[email protected]>

There is no point in trying to create a dlist entry for planes that have a 0 crtc size, and it can also cause grief in the vc6 dlist generation as it takes width-1 and height-1, causing wrap around. Drop these planes. Signed-off-by: Dave Stevenson <[email protected]>

2712D0 removed alpha_mode from control word 2 for choosing fixed alpha and replaced it with the previously reserved value of 3 in alpha_mask. Handle this to fix corrupt desktop when using X on 2712D0 Signed-off-by: Dom Cobley <[email protected]>

We have a read-modify-write race when updating SCALER_DISPCTRL for underrun and end-of-frame interrupts. Ideally it would be fixed via a spinlock or similar, but that will require a reasonable amount of study to ensure we don't get deadlocks. The underrun reporting is only for debug, so disable it for now. Signed-off-by: Dave Stevenson <[email protected]>

The SDIO_CFG register SD_PIN_SEL conflates two settings - whether eMMC HS or SD UHS timings are applied to the interface, and whether or not the card-detect line is functional. SD_PIN_SEL can only be changed when the SD clock isn't running, so add a bcm2712-specific clock setup. Toggling SD_PIN_SEL at runtime means the integrated card-detect feature can't be used, so this controller needs a cd-gpios property. Also fix conditionals for usage of the delay-line PHY - no-1-8-v will imply no bits set in hsemmc_mask or uhs_mask, so remove it. Signed-off-by: Jonathan Bell <[email protected]>

The code was reducing the number of components by one when we were not blending with alpha. But that only makes sense if the components include alpha. For YUV, we were reducing the number of components for Y from one to zero which resulted in no lbm space being allocated. Fixes: raspberrypi#5912 Signed-off-by: Dom Cobley <[email protected]>

If enabled, DMA_BOUNCE_UNALIGNED_KMALLOC causes the swiotlb buffers (64MB, by default) to be allocated, even on systems where the DMA controller can reach all of RAM. This is a huge amount of RAM to waste on a device with only 512MB to start with, such as the Zero 2 W. See: raspberrypi#5975 Signed-off-by: Phil Elwell <[email protected]>

This patch adds the device ID for the BCM4343A2 module, found e.g. in the Infineon (Cypress) CYW43439 chip. The required firmware file is named 'BCM4343A2.hcd'. Signed-off-by: Phil Elwell <[email protected]>

Add this as a value for enum_drm_connector_tv_mode, represented by the string "Mono", to generate video with standard timings but no colour encoding or bursts. Define it to have no pedestal (since only NTSC-M calls for a pedestal). Change default mode creation to acommodate the new tv_mode value which comprises both 525-line and 625-line formats. Signed-off-by: Nick Hollinghurst <[email protected]>

The VEC supports not producing colour bursts for monochrome output. It also has an option for disabling the chroma input to remove chroma from the signal. Now that there is a DRM_MODE_TV_MODE_xx defined for monochrome, plumb this in. Signed-off-by: Dave Stevenson <[email protected]>

PLL_AUDIO has a ternary divider (a copy of the secondary divider) and PLL_VIDEO has a primary phased output. Signed-off-by: Jonathan Bell <[email protected]>

Add ALSA jack detection to the vc4-hdmi audio driver so userspace knows when to add/remove HDMI audio devices. Signed-off-by: David Turner <[email protected]>

The newer Raspberry Pi 5" and 7" panels have a slightly different register map to the original one. Add a new driver for this regulator. Signed-off-by: Dave Stevenson <[email protected]>

i2c_mux_add_adapter takes a force_nr parameter that allows an explicit bus number to be associated with a channel. However, only i2c-mux-reg and i2c-mux-gpio make use of it. To help with situations where it is desirable to have a fixed, known base address for the channels of a mux, create a "base-nr" property. When force_nr is 0 and base-nr is set and non-zero, form a force_nr value from the sum of base-nr and the channel ID. Signed-off-by: Phil Elwell <[email protected]>

I'm sure the dtc warnings mean well, but overlays don't have enough context for the checkers to give meaningful results. Signed-off-by: Phil Elwell <[email protected]>

In deep sleep mode (DS1) ARM is off and once exit trigger comes than mailbox Interrupt comes to host and whole reinitiation should be done in the ARM to start TX/RX. Also fix below issus for DS1 exit: 1. Sent Tx Control frame only after firmware redownload complete (check F2 Ready before sending Tx Control frame to Firmware) 2. intermittent High DS1 TX Exit latency time (almost 3sec) ==> This is fixed by skipping host Mailbox interrupt Multiple times (ulp state mechanism) 3. RX GlOM save/restore in Firmware 4. Add ULP event enable & event_msgs_ext iovar configuration in FMAC 5. Add ULP_EVENT_RECV state machine for sbwad support 6. Support 2 Byte Shared memory read for DS1 Exit HUDI implementation Signed-off-by: Praveen Babu C <[email protected]> Signed-off-by: Naveen Gupta <[email protected]> [Merge from 4.14.77 to 5.4.18; set BRCMF_SDIO_MAX_ACCESS_ERRORS to 20] Signed-off-by: Chi-hsien Lin <[email protected]> JIRA: SWWLAN-135583 JIRA: SWWLAN-136577

1. If firmware supports 4-way handshake offload but not supports DPP 4-way offload, when user first connects encryption network, driver will set "sup_wpa 1" to firmware, but it will further result in DPP connection failure since firmware won't send EAPOL frame to host. 2. Fix DPP AP mode handling action frames. 3. For some firmware without fwsup support, the join procedure will be skipped due to "sup_wpa" iovar returning not-support. Check the fwsup feature before do such iovar. Signed-off-by: Kurt Lee <[email protected]> Signed-off-by: Double Lo <[email protected]> Signed-off-by: Chi-hsien Lin <[email protected]>

Firmware has SME functionality but would like the userspace to handle SAE authentication. This patch adds support for such an external SAE authentication mechanism in station mode. Signed-off-by: Chung-Hsien Hsu <[email protected]> Signed-off-by: Chi-hsien Lin <[email protected]>

Commit 7d239fb broke 802.1X authentication by setting profile->use_fwsup = NONE whenever PSK is not used. However 802.1X does not use PSK and requires profile->use_fwsup set to 1X, or brcmf_cfg80211_set_pmk() fails. Fix this by checking that profile->use_fwsup is not already set to 1X and avoid setting it to NONE in that case. Fixes: 7d239fb (brcmfmac: Fix interoperating DPP and other encryption network access) Fixes: raspberrypi#5964

Update the overlay build rules to use the dtbs-list mechanism. Also include the README, and don't set the executable bits. Signed-off-by: Phil Elwell <[email protected]>

Application class A2 cards require CQ to be enabled to realise their stated performance figures. Add support to enable/disable card CQ via the Performance Enhancement extension register, and cater for the slight differences in command set versus eMMC. Signed-off-by: Jonathan Bell <[email protected]>

CQHCI keeps track of tags in flight with internal timers, so the clock frequency driving the timer needs to be specified. The config registers default to 0 (100kHz) which means timeouts will be significantly shorter than they should be. Assume the timer clock comes from the controller base clock. Signed-off-by: Jonathan Bell <[email protected]>

The Performance Extension register is regularly accessed in a hot path to do write cache flushes. Don't invoke kmalloc/kfree for every access, preallocate a 512B buffer for this purpose. Also remove an unused alloc in sd_enable_cache(). Signed-off-by: Jonathan Bell <[email protected]>

Add a LED_FULL trigger equivalent to mmc_start_request() in mmc_cqe_start_req(), otherwise it stays off forever. Signed-off-by: Jonathan Bell <[email protected]>

For unknown reasons the controller seems to reset the idle polling timer interval on CQE enable/disable to 8 clocks which is extremely short. Just use the reset value in the eMMC spec (4096 clock periods which at 200MHz is ~20uS). Signed-off-by: Jonathan Bell <[email protected]>

The default was to have enable_bg_fill disabled and the first plane set it if it wasn't opaque and covering the whole screen. However that meant that if no planes were enabled, then the background fill wasn't enabled, and would give a striped output from the uninitialised output buffer. Initialise it to enabled to avoid this. Signed-off-by: Dave Stevenson <[email protected]>

The eMMC spec says that in certain circumstances the controller can't respond to a halt request - in practice, this occurs if a CMD timeout happens (card went away/crashed). Clear the halt request by writing 0 to CQHCI_CTL. Also fix a logic error testing for halt in cqhci_request. Signed-off-by: Jonathan Bell <[email protected]>

Certain status bits in these registers may need polling outside of SD-specific code. Export in sd_ops.h Signed-off-by: Jonathan Bell <[email protected]>

Don't attempt to turn on CQ if the other mandatory features are not indicated as supported by the card. Also make sure that the register write actually stuck, as some cards claim support but never report back that the queue engine is enabled. Signed-off-by: Jonathan Bell <[email protected]>

Also report the card's supported queue depth in the message log. Signed-off-by: Jonathan Bell <[email protected]>

The spec allows for up to two 512-byte pages to be allocated for the Extension Register General Info block, so allocate accordingly. Signed-off-by: Jonathan Bell <[email protected]>

Newer versions of the DesignWare I2C block support the detection of stuck signals, and a mechanism to recover from them. Add the required software support to the driver. This change was prompted by the observation that reading a single byte from register 0 of a VEML7700 seems to cause it to issue an ACK too early, and the controller to complain about losing arbitration. There is a suspicion that this may be a more widespread problem, but at least this patch prevents the bus from locking up. See: raspberrypi#6057 Signed-off-by: Phil Elwell <[email protected]>

In the absence of a value in Device Tree, set the SDA hold time to half the SCL low time. Signed-off-by: Phil Elwell <[email protected]>

This supports reading and writing OTP using the firmware mailbox interface. It needs supporting firmware to run. Signed-off-by: Dom Cobley <[email protected]>

Applying MMC_QUIRK_BROKEN_SD_CACHE is broken, as the card's extended registers are parsed prior to the quirk being applied in mmc_blk. Split this out into an SD-specific list of quirks and apply in mmc_sd_init_card instead. Fixes: c467c8f ("mmc: Add MMC_QUIRK_BROKEN_SD_CACHE for Kingston Canvas Go Plus from 11/2019") Signed-off-by: Jonathan Bell <[email protected]>

Samsung EVO Plus, Pro Plus and Evo Ultimate cards of this era appear to have a broken cache-flush implementation when operating in CQ mode. Unfortunately the cards seem to use a separate CID name string for every variant and capacity, so nobble the cache feature for this MANFID, OEMID and year. Turning this off seems to have negligible impact on random-write throughput in non-CQ mode. Signed-off-by: Jonathan Bell <[email protected]>

Enhanced Strobe and clock gating are set in the SDHCI_VENDOR register, so make the driver aware it needs to do this for this controller. Signed-off-by: Jonathan Bell <[email protected]>

CI builds are done with debug info disabled, but this removes some members from struct module. This causes builds to fail if there is an ABI reference for the current ABI. Define these members unconditionally, so that there is no ABI change.

Get rid of the remaining node.js warnings by updating the actions. Signed-off-by: Phil Elwell <[email protected]>

The legacy stack had an option to have a GPIO track frame start and end events to give basic synchronisation to the incoming image stream. https://forums.raspberrypi.com/viewtopic.php?t=190314 Replicate this in the kernel Unicam driver. Signed-off-by: Dave Stevenson <[email protected]>

This code: for_each_sg(sgl, sg, sg_len, i) num_sgs += DIV_ROUND_UP(sg_dma_len(sg), axi_block_len); determines how many hw_desc are allocated. If sg_dma_len(sg)=0 we don't allocate for this sgl. However in the next loop, we will increment loop for this case, and loop gets higher than num_sgs and we trample memory. Signed-off-by: Dom Cobley <[email protected]>

The 8-bit and 16-bit mono formats were missing the appropriate remap entries in the format table. Signed-off-by: Naushir Patuck <[email protected]>

The intention of the vc4.force_hotplug setting is to ignore hotplug completely. It can be used when a display toggles hotplug when switching AV inputs, going into standby or changing a KVM switch, and some side effect of that is unwanted. It turns out while vc4.force_hotplug currently makes hotplug always read as asserted, that isn't enough to stop drm doing lots of stuff, including re-reading the edid. An example of what drm does with a hotplug deasert/assert and vc4.force_hotplug=1 currently is: https://paste.debian.net/hidden/dc07434b/ That is unwanted. Lets ignore the hotplug interrupt completely so drm is blissfully unaware of the hotplug change. Signed-off-by: Dom Cobley <[email protected]>

Escape clock divider was fixed at 5, which is correct at 800Mbps/lane but increasingly out of spec for higher rates. Compute it correctly. High speed timeout was fixed at 5*512 == 2560 byte-clocks per lane. Compute it conservatively to be 8/7 times the line period (assuming there will be a transition to LP some time during each scanline?) keeping the old value as a lower bound. Increase LPRX TO to 1024, and BTA TO to 0xb00 (same value as in bridge/synopsys/dw-mipi-dsi). (No change to LP_CMD_TIM. To do: compute this correctly.) Signed-off-by: Nick Hollinghurst <[email protected]>

"rotation" is listed as a standard property of panels in panel-common.yaml, therefore it would be logical to process that from within the core code should a panel driver not implement the get_orientation hook. Call of_drm_get_panel_orientation from drm_connector_set_orientation_from_panel to get that information. This removes the need for any boiler-plate in panel drivers for calling drm_connector_set_orientation_from_panel or drm_connector_set_panel_orientation. Signed-off-by: Dave Stevenson <[email protected]>

The framework now handles reading orientation from DT, therefore remove the custom get_orientation hook from panel-simple. Signed-off-by: Dave Stevenson <[email protected]>

Support a wider range of pixel clock rates. The driver will round pixclock up to 108MHz/n but tries to honour the desired image width and position (of the centre of the display relative to HSYNC_STARTs). This adds complexity but removes the need for separate 13.5MHz and 15.428MHz modes. Support "fake" double-rate progressive modes (in which only every 2nd scanline is displayed). To work around aspect ratio issues. Add Monochrome TV mode support. Add "vintage" modes (544x380i for System A; 848x738i for System E) when configured for Monochrome. Add a way to create a "custom" display mode from a module parameter. Signed-off-by: Nick Hollinghurst <[email protected]>

The autodetection of resolution/timing by the TC358762 can lead to the display being shifted by a pixel or two. Program the TC358762 with the requested mode timing so that it can reproduce it accurately. Signed-off-by: Dave Stevenson <[email protected]>

Reverts 8a4b2fc ("drm/bridge: tc358762: Split register programming from pre-enable to enable") as we want the config commands sent before video starts. Signed-off-by: Dave Stevenson <[email protected]>

The initialisation sequence differs slightly from the documentation in that the clocks are meant to be running before resets and similar. Signed-off-by: Dave Stevenson <[email protected]>

vc4_dsi_bridge_disable wasn't resetting things during shutdown, so add that in. Signed-off-by: Dave Stevenson <[email protected]>

The block must be enabled for the FIFO resets to be actioned, so ensure this is the case. Signed-off-by: Dave Stevenson <[email protected]>

DSI0 is misbehaving and needs to action things on vblank to work around it. Add a new hook to call across during vblank. Signed-off-by: Dave Stevenson <[email protected]>

The pixel to byte FIFO appears to not always reset correctly, which can lead to colour errors and/or horizontal shifts. Reset on every vblank to work around the issue. Signed-off-by: Dave Stevenson <[email protected]>

DSI0 can take the clock from either PLLA or PLLD. PLLA is the default muxing, but PLLD is considered the more stable. Switch to using PLLD. Signed-off-by: Dave Stevenson <[email protected]>

The 7inch panel is one line off the screen both horizontally and vertically. Alter the panel mode to correct this. Signed-off-by: Dave Stevenson <[email protected]>

The Toshiba bridge is very fussy and doesn't like the CM3 output when being told to produce a 27.777MHz pixel clock, which is an almost perfect match to the DSI link integer divider. Increasing to 30MHz will switch the DSI link from 333MHz to 400MHz and makes the bridge happy with the same video timing as works on Pi4. (Pi4 will be using a link frequency of 375MHz due to a 3GHz parent PLL). Signed-off-by: Dave Stevenson <[email protected]>

The TC358762 bridge and panel decodes the mode differently on DSI0 to DSI1 for no obvious reason, and results in a shift off the screen. Whilst it would be possible to change the compatible used for the panel, that then messes up Pi5. As it appears to be restricted to vc4 DSI0, fix up the mode in vc4_dsi. Signed-off-by: Dave Stevenson <[email protected]>

Adds a shutdown function to turn off the backlight, bridge, and touch controller on shutdown. Signed-off-by: Dave Stevenson <[email protected]>

This new format corresponds to the Raspberry Pi legacy DPI mode 3. Signed-off-by: Nick Hollinghurst <[email protected]>

Having accepted the upstream change to add the persist_gpio_outputs parameter, make it true by default. See: raspberrypi#6117 Signed-off-by: Phil Elwell <[email protected]>

vc4_disable_vblank assumed that vc4_encoder was always assigned, which isn't guaranteed. If it isn't assigned then disable the interrupt anyway as it's not connected. raspberrypi#6146 Fixes: 63c0bcc ("drm/vc4: Add option to call from crtc to encoder on vblank") Signed-off-by: Dave Stevenson <[email protected]>

Even when configured to use only gpiod CS lines, the DW SPI controller still expects a bit to be set in the SER register, otherwise transfers stall. For the csgpiod case, nominate bit 0 for the job. See: raspberrypi#6159 Signed-off-by: Phil Elwell <[email protected]>

Add shutdown and remove hooks so that the panel gets powered off with the system. Signed-off-by: Dave Stevenson <[email protected]>

As with many microcontrollers, the panel wants to use clock stretching during a read so that the appropriate return value can be generated and programmed into the hardware. With Pi0-3 really not supporting clock stretching, this resulted in the panel firmware dying. Insert a delay between the write and the read to give the firmware a chance to generate the relevant return value. Signed-off-by: Dave Stevenson <[email protected]>

There are no MEDIA_BUS_FMT_* defines for GRB or BRG, and adding them is a pain. Add a DT override to allow setting the order. Signed-off-by: Dave Stevenson <[email protected]>

The stride value reported for output image buffers should be at least as large as any value that was passed in by the caller (subject to correct alignment for the pixel format). If the value is zero (meaning no value was passed), or is too small, the minimum acceptable value will be substituted. Signed-off-by: David Plowman <[email protected]>

If a set of read requests are issued by an endpoint, they are streamed into a resynchronisation FIFO prior to exiting the RC. This FIFO has an edge case where it can drop QoS for a request to 0 if there's a single outstanding read request in the FIFO, and another is pushed when the FIFO is popped. Requests with a QoS of 0 can take hundreds of microseconds to complete. By adding an experimentally-determined amount of backpressure on the pop side, the critical level transition can largely be avoided. Signed-off-by: Jonathan Bell <[email protected]>

The naming of backlight devices is not terribly useful for associating a backlight controller with a display (assuming it is attached to one). Add a sysfs node that will return a display name that can be set by other subsystems. Signed-off-by: Dave Stevenson <[email protected]>

Pass the DRM connector name to any configured backlight device so that userspace can associate the two items. Ideally this should be in drm_panel, but it is bridge/panel that creates the drm_connector and therefore knows the name. Signed-off-by: Dave Stevenson <[email protected]>

Add version 4.17.1 of the Hailo PCIe device drivers. Sourced from https://github.com/hailo-ai/hailort-drivers/ Signed-off-by: Naushir Patuck <[email protected]>

…mbols

This reverts commit 980249a.

Add helpers to set and get vchiq driver data. vchiq_set_drvdata() and vchiq_get_drvdata() wraps dev_set_drvdata() and dev_get_drvdata() respectively. Signed-off-by: Umang Jain <[email protected]> Signed-off-by: Kieran Bingham <[email protected]>

The vchiq_connected.h header was removed in f875976 ("staging: vc04_services: Drop vchiq_connected.[ch] files") to simplify the implementation. Update the vc_sm driver accordingly which can still use the same functions through the vchiq_arm.h header declarations. Fixes: b1ab7a0 ("staging: vc04_services: Add new vc-sm-cma driver") Signed-off-by: Kieran Bingham <[email protected]>

Drop the include directive. They can break the build, when one only wants to build a subdirectory. Replace with "../" for the includes in the vc_sm files instead. The fix is equivalent to the four patches between 29d49a7 ("staging: vc04_services: bcm2835-audio: Drop include Makefile directive")...2529ca2 ("staging: vc04_services: interface: Drop include Makefile directive") Fixes: b1ab7a0 ("staging: vc04_services: Add new vc-sm-cma driver") Suggested-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Kieran Bingham <[email protected]>

Drop the include directive. They can break the build, when one only wants to build a subdirectory. Replace with "../" for the includes in the bcm2835-isp instead. The fix is equivalent to the four patches between 29d49a7 ("staging: vc04_services: bcm2835-audio: Drop include Makefile directive")...2529ca2 ("staging: vc04_services: interface: Drop include Makefile directive") Fixes: c8f89c9 ("staging: vc04_services: ISP: Add a more complex ISP processing component") Suggested-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Kieran Bingham <[email protected]>

Drop the include directive. They can break the build, when one only wants to build a subdirectory. Replace with "../" for the includes in the bcm2835-v4l2-codec instead. The fix is equivalent to the four patches between 29d49a7 ("staging: vc04_services: bcm2835-audio: Drop include Makefile directive")...2529ca2 ("staging: vc04_services: interface: Drop include Makefile directive") Fixes: afaec52 ("staging: vc04_services: Add a V4L2 M2M codec driver") Suggested-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Kieran Bingham <[email protected]>

Register the vcsm rive with the vchiq_bus_type instead of useing the platform driver/device. Signed-off-by: Kieran Bingham <[email protected]>

Register the bcm2835-v4l2-isp driver with the vchiq_bus_type instead of using the platform driver/device. Signed-off-by: Kieran Bingham <[email protected]>

Signed-off-by: Kieran Bingham <[email protected]>

…icate symbols" This reverts commit a095fe8.

Remove the duplicate definitions we picked up in the move to 6.10. At a later date it's probably worth removing the dependencies on bcm270x.dtsi, etc. Signed-off-by: Phil Elwell <[email protected]>

The rpi-otp driver uses a virtualised, OTP-relative addressing scheme. However, when instance nodes are children of "/soc" they appear to be addressable directly by the host, which is wrong (but not in a way which causes an error unless one goes looking for one). Add a wrapper (bus) node without a "ranges" property to make the separation clear. See: raspberrypi#6196 Signed-off-by: Phil Elwell <[email protected]>

Signed-off-by: Phil Elwell <[email protected]>

* Re-expose some dmi APIs for use in VCSM

Signed-off-by: Phil Elwell <[email protected]>

After the decision to use bcm2711 compatible for upstream, we should switch all accepted compatibles to bcm2711. So we can boot with one DTB the down- and the upstream kernel. Signed-off-by: Stefan Wahren <[email protected]>

Now that V4L2_PIX_FMT_Y12P is defined, allow passing raw 12bit mono packed data through the peripheral. Signed-off-by: Dave Stevenson <[email protected]>

Now that V4L2_PIX_FMT_Y14 and V4L2_PIX_FMT_Y14P are defined, allow passing 14bit mono data through the peripheral. Signed-off-by: Dave Stevenson <[email protected]>

Now that the 14bit non-packed Bayer formats are defined, add them into the supported formats lookup table. Signed-off-by: Dave Stevenson <[email protected]>

I225-V network adapters have a buggy ROM that won't complete internal initialisation if (at least) BAR0 has an assigned address of 0x0. Add a parameter to the pciex1-compat-pi5 overlay to make outbound addresses start at 2GB. Signed-off-by: Jonathan Bell <[email protected]>

Update rpi-simple-soundcard.c with 384kHz support.

Polarity bits were only ever set and never cleared. Make sure they can also be cleared. Signed-off-by: Michiel Vanbiervliet <[email protected]>

This reverts commit faa3867.

An attempt to fix the include paths - they look reasonable, but the GitHub auto-builds fail. Signed-off-by: Phil Elwell <[email protected]>

The current configs enable fou as a module, but fou is not very useful without CONFIG_NET_FOU_IP_TUNNELS, because it can't be used to actually create tunnels: $ sudo ip fou add port 12345 ipproto ipip $ sudo ip link add name fou1 type ipip local any remote 8.8.8.8 \ encap fou encap-sport auto encap-dport 12345 RTNETLINK answers: Invalid argument Enable the option by default. This does not increase memory footprint because fou is not loaded by default. Uncompressed module size goes from 26.3KiB to 32.5KiB. After this change, things work: $ sudo ip fou add port 12345 ipproto ipip $ sudo ip link add name fou1 type ipip local any remote 8.8.8.8 \ encap fou encap-sport auto encap-dport 12345 $ ip link show fou1 8: fou1@NONE: <POINTOPOINT,NOARP> mtu 1472 qdisc noop state DOWN [...] link/ipip 0.0.0.0 peer 8.8.8.8 Signed-off-by: Lorenzo Colitti <[email protected]>

The attached PHY performs parameter validation, so the switch from HS200 to HS (before selecting HS400/HS400es) with a 200MHz clock fails to update pad timings and results in CRC errors from the card. Underclocking the interface is safe, so do that in the downgrade callback. Signed-off-by: Jonathan Bell <[email protected]>

Enhanced strobe means HS200 training can be skipped. Signed-off-by: Jonathan Bell <[email protected]>

SD cards perform cache flushes by a CMD49 extension register write - which needs to be started from the SDHCI command/argument registers and not a CQHCI slot. Host access to SD/CQ registers should be exclusive to one or the other, so issue a halt before doing the command. Signed-off-by: Jonathan Bell <[email protected]>

This gains about 8-12% sequential write speed with the fastest SD/eMMC cards, and Class A1/A2 card sequential performance is only assured with a 4MiB write length. Signed-off-by: Jonathan Bell <[email protected]>

Add a custom property "Output format" that allows the overriding of the default colourspace choice in the way that the old firmware hdmi_pixel_encoding property did. If the chosen format is not supported, then it will still drop back to the older behaviour. This won't be acceptable to upstream, but it adds back the missing functionality of hdmi_pixel_encoding. Signed-off-by: Dave Stevenson <[email protected]>

Following [1], it becomes harder for the CPU DAI to know the correct BCLK ratio. We can either bake the same knowledge into the sound card driver, or implement and use set_bclk_ratio on the codec. This commit does the latter. [1] commit c89e652 ("ASoC: da7213: Add support for mono, set frame width to 32 when possible") Signed-off-by: Phil Elwell <[email protected]>

To ensure that the CPU DAI and codec agree over the BCLK ratio, impose a fixed value of 64 on both of them. Signed-off-by: Phil Elwell <[email protected]>

Add two new DT properties: * microchip,eee-enabled - a boolean to enable EEE * microchip,tx-lpi-timer - time in microseconds to wait before entering low power state Signed-off-by: Phil Elwell <[email protected]>

Disabling tx_lpi or eee should not cause the value of tx_lpi_timer to be lost, even though it is not useful until they are re-enabled. Signed-off-by: Phil Elwell <[email protected]>

The platform model originally handled the DMA mask. Now that we are on the vchiq_bus we need to explicitly set this. Signed-off-by: Kieran Bingham <[email protected]>

Include Rados block device (RBD) support in standard kernel builds, a common companion for CEPH which is included. See: raspberrypi#6224 Signed-off-by: Phil Elwell <[email protected]>

If the controller is being reset, then the CQE needs to be reset as well. For removable cards, CQHCI_SSC1 must specify a polling mode (CBC=0) otherwise it's possible that the controller stops emitting periodic CMD13s on card removal, without raising an error status interrupt. Signed-off-by: Jonathan Bell <[email protected]>

Recovery claims the MMC card so the card-detect work gets significantly delayed - leading to lots of error recovery loops that can never do anything but fail. Explicitly detect the card after CQE has halted and bail if it's not there. Also ratelimit a not-very-descriptive warning - one occurrence in dmesg is enough to signal that something is amiss. Signed-off-by: Jonathan Bell <[email protected]>

fix: Fix wrong Pironman 5 ir default pin number fix: Change space indentation to tab Signed-off-by: Cavon Lee <[email protected]>

Fixes: 0328609("drivers/gpio: Add a driver that wraps the PWM API as a GPIO controller") Signed-off-by: Ratchanan Srirattanamet <[email protected]>

Ensure that the various options of modules vs builtin results in being able to call into the backlight code. raspberrypi#6198 Fixes: 573f8fd ("drm/bridge: panel: Name an associated backlight device") Signed-off-by: Dave Stevenson <[email protected]>

Both bcm283x-rpi-csi1-2lane.dtsi and bcm283x-rpi-lan7515.dtsi are linked to "../arm/boot/dts/" instead of "../arm/boot/dts/broadcom", so the links are broken. Fixes: d060fc0 ("BCM2708: Add core Device Tree support") Signed-off-by: Álvaro Fernández Rojas <[email protected]>

6.10 changes the KConfig settings for SC16IS7XX UARTS. Update the RPi defconfigs to retain the SPI and I2C variants. Signed-off-by: Phil Elwell <[email protected]>

The rework in fs/ntfs3: Reduce stack usage changes log->page_size but doesn't change the associated log->page_mask and log->page_bits. That results in the bytes value in read_log_page getting a negative value, which is bad when it is passed to memcpy. The kernel panic can be observed when connecting an ntfs formatted drive that has previously been connected to a Windows machine to a Raspberry Pi 5, which by defauilt uses a 16K kernel pagesize. Fixes: 865e7a7 ("fs/ntfs3: Reduce stack usage") Signed-off-by: Dom Cobley <[email protected]>

The kernel C standard changed in 5.18. Remove a layer of indirection around the FIQ bounce buffers, be consistent with pointers to FIQ bounce buffers, and remove open-coded 32-bit clamping of DMA addresses. Also remove a pointless fiq_state initialisation loop. Signed-off-by: Jonathan Bell <[email protected]>

The Y10P, Y12P and Y14P format variants are packed according to the RAW10, RAW12 and RAW14 formats as defined by the MIPI CSI-2 specification. Document it. Signed-off-by: Jacopo Mondi <[email protected]> Reviewed-by: Laurent Pinchart <[email protected]> Reviewed-by: Naushir Patuck <[email protected]>

Add BGR48 and RGB48 16-bit per component image formats. Signed-off-by: Jacopo Mondi <[email protected]> Reviewed-by: Kieran Bingham <[email protected]> Reviewed-by: Naushir Patuck <[email protected]>

Add the Raspberry Pi PiSP Back End uAPI header. The header defines the data type used to configure the PiSP Back End ISP. The detailed description of the types and of the ISP configuration procedure is available at https://datasheets.raspberrypi.com/camera/raspberry-pi-image-signal-processor-specification.pdf Signed-off-by: Jacopo Mondi <[email protected]>

Add format description for the PiSP Back End configuration parameter buffer. Signed-off-by: Jacopo Mondi <[email protected]> Reviewed-by: Naushir Patuck <[email protected]>

Document the Raspberry Pi compressed RAW Bayer formats. The compression algorithm description is provided by Nick Hollinghurst <[email protected]> from Raspberry Pi. Signed-off-by: Jacopo Mondi <[email protected]> Reviewed-by: Naushir Patuck <[email protected]>

Add bindings for the Raspberry Pi PiSP Back End memory-to-memory image signal processor. Datasheet: https://datasheets.raspberrypi.com/camera/raspberry-pi-image-signal-processor-specification.pdf Signed-off-by: Jacopo Mondi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Naushir Patuck <[email protected]>

Add documentation for the PiSP Back End memory-to-memory ISP. Signed-off-by: Jacopo Mondi <[email protected]>

Backport to rpi-6.6.y the mainline version of the PiSP BE driver. The backported version of the driver corresponds to the one available at: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Jacopo Mondi <[email protected]>

The pisp_be_config.h uAPI header file contains a bit-field definition that uses the BIT() helper macro. As the BIT() identifier is not defined in userspace, drop it from the uAPI header. Fixes: c6c49ba ("media: uapi: Add Raspberry Pi PiSP Back End uAPI") Signed-off-by: Jacopo Mondi <[email protected]> Reviewed-by: Tomi Valkeinen <[email protected]>

Add definition and test for 32-bits image formats to the pisp_common.h uAPI header. Signed-off-by: Jacopo Mondi <[email protected]>

The macro used to inspect an image format characteristic use a mixture of capitalized and non-capitalized letters, which is rather unusual for the Linux kernel style. Capitalize all identifiers. Signed-off-by: Jacopo Mondi <[email protected]>

The order of the members of pisp_be_tiles_config is relevant as the driver logic assumes 'config' to be at offset 0. Re-sort the member to match the driver's expectations. Fixes: c6c49ba ("media: uapi: Add Raspberry Pi PiSP Back End uAPI") Signed-off-by: Jacopo Mondi <[email protected]>

Complete the pisp_be_config strcture by adding fields that even if not written to the HW are relevant to complete the uAPI and put it in par with the BSP driver. Fixes: c6c49ba ("media: uapi: Add Raspberry Pi PiSP Back End uAPI") Signed-off-by: Jacopo Mondi <[email protected]>

Re-introduce multi-context support that was dropped from the mainline driver version. Signed-off-by: Jacopo Mondi <[email protected]>

Offset the backend dev-nodes starting at /dev/video20 onwards to maintain backward compatibility with the pre-upstreamed kernel driver. Signed-off-by: Naushir Patuck <[email protected]>

The camera regulator GPIO can be used for other purposes, so the camN_reg override to allow disabling is potentially useful on any platform. camN_gpio is less useful, but isn't invalid. Move these overrides from the CM dt files to bcm270x-rpi.dtsi and bcm2712-rpi.dtsi. Signed-off-by: Dave Stevenson <[email protected]>

Add YAML device tree bindings for the Raspberry Pi RP2040 GPIO Bridge. Signed-off-by: Richard Oliver <[email protected]>

The Raspberry Pi RP2040 GPIO bridge is an I2C-attached device exposing both a Tx-only SPI controller, and a GPIO controller. Due to the relative difference in transfer rates between standard-mode I2C and SPI, the GPIO bridge makes use of 12 MiB of non-volatile storage to cache repeated transfers. This cache is arranged in ~8 KiB blocks and is addressed by the MD5 digest of the data contained therein. Optionally, this driver is able to take advantage of Raspberry Pi RP1 GPIOs to achieve faster than I2C data transfer rates. Signed-off-by: Richard Oliver <[email protected]>

The snps,block-size DT property declares the maximum block size for each channel of the dw-axi-dmac. However, the driver ignores these when setting max_seg_size and uses MAX_BLOCK_SIZE (4096) instead. To take advantage of the efficiencies of larger blocks, calculate the minimum block size across all channels and use that instead. See: raspberrypi#6256 Signed-off-by: Phil Elwell <[email protected]>

Command Queueing requires Write Cache and Power off Notification support from the card - but using the write cache forms a contract with the host whereby the card expects to be told about impending power-down. The implication is that (for performance) the card can do unsafe things with pending write data - including reordering what gets committed to nonvolatile storage at what time. Exposed SD slots and platforms powered by hotpluggable means (i.e. Raspberry Pis) can't guarantee that surprise removal won't happen. To limit the scope for cards to invent new ways to trash filesystems, limit pending writes to 1 (equivalent to the non-CQ behaviour). Signed-off-by: Jonathan Bell <[email protected]>

Leaving card->max_posted_writes unintialised was a bad thing to do. Also, cqe_enable is 1 if hsq is enabled as hsq substitutes the cqhci implementation with its own. Signed-off-by: Jonathan Bell <[email protected]>

Commit 485d942 ("mmc: sdhci-brcmstb: check R1_STATUS for erase/trim/discard") introduced a new flag and defaulted to disabling card busy detection across all platforms with this controller. This is required for IO voltage switching, as the card drives CMD low while the switch is in progress. Signed-off-by: Jonathan Bell <[email protected]>

This reverts commit dd7a154.

The firmware advertises its features as a string of words separated by spaces. Ensure that feature names are only matched in their entirety. Signed-off-by: Phil Elwell <[email protected]>

The Cypress firmwares use "extsae" to indicate wpa_supplicant-hosted SAE/WPA3. Signed-off-by: Phil Elwell <[email protected]>

support sae executed in wpa_supplicant and offload 4-way handshake offload. Signed-off-by: Chien-Chia Chen <[email protected]> JIRA: SWWLAN-142424

This reverts commit a3d53c8.

Define two new RP1 clocks, representing the MIPI DSI byteclock sources for the dividers used to generate MIPI[01] DPI pixel clocks. (Previously they were represented by "fake" fixed clocks sources). Signed-off-by: Nick Hollinghurst <[email protected]>

Add a new class of clocks to RP1 to represent clock sources whose frequency changes at run-time as a side-effect of some other driver. Specifically this is for the two MIPI DSI byte-clock sources. Signed-off-by: Nick Hollinghurst <[email protected]>

Remove the "dummy" 72MHz fixed clock sources and associate DSI driver with the new "variable" clock sources now defined in RP1 clocks. Also add PLLSYS clock to DSI, which it will need as an alternative clock source in those cases where DPI pixclock > DSI byteclock. Signed-off-by: Nick Hollinghurst <[email protected]>

To support 4 lanes, re-parent DPI clock source between DSI byteclock (using the new "variable sources" defined in clk-rp1) and PLL_SYS. This is to cover cases in which byteclock < pixclock <= 200MHz. Tidying: All frequencies now in Hz (not kHz), where DSI speed is now represented by byteclock to simplify arithmetic. Clamp DPI and byte clocks to their legal ranges; fix up HSTX timeout to avoid an unsafe assumption that it would return to LP state for every scanline. Because of RP1's clock topology, the ratio between DSI and DPI clocks may not be exact with 3 or 4 lanes, leading to slightly irregular timings each time DSI switches between HS and LP states. Tweak to inhibit LP during Horizontal BP when sync pulses were requested. Signed-off-by: Nick Hollinghurst <[email protected]>

It is pointless having the bcm2712 family of dts files and rp1.dtsi in the arch/arm directory tree, since they then require placeholders to include them in arch/arm64 where they are built. The files have no dependencies on other files in the arch/arm tree, so simply move them here. Signed-off-by: Phil Elwell <[email protected]>

CM5 Lite DTBs require minor changes compared to the "heavy" variants. Signed-off-by: Phil Elwell <[email protected]>

Move the aliases and overrrides shared by Pi 5 and CM5 into bcm2712-rpi.dtsi. Signed-off-by: Phil Elwell <[email protected]>

Drop some duplicate declarations, and also delete #interrupt-cells from gio_aon for Pi 5B (it's already done for CM5). Signed-off-by: Phil Elwell <[email protected]>

The bootloader patches the DT with the correct model string, but it is better not to rely on that by setting it from the start. Signed-off-by: Phil Elwell <[email protected]>

Enabling CONFIG_BRIDGE_VLAN_FILTERING allows bridges to automatically receive and forward packets based on the 802.1q VLAN information and the device/port configuration. See: raspberrypi#6275 Signed-off-by: Xavier L. <[email protected]>

Whilst the Unicam driver has now been upstreamed it only supports configuration via Media Controller (not driven from the /dev/videoN node), which makes life significantly harder for simple devices such as mono sensors, and HDMI or analogue video to CSI2 bridge chips (eg TC358743 and ADV7282M). Fix up the downstream driver so that it builds, reinstate the links from Kconfig and Makefile to it, and give it a new Kconfig name (VIDEO_BCM2835_UNICAM_LEGACY). Signed-off-by: Dave Stevenson <[email protected]>

The upstream Unicam driver doesn't support a mode that doesn't use the Media Controller API to configure the pipeline. The old downstream driver is still being built with an alternate compatible of "brcm,bcm2835-unicam-legacy", so replace the "brcm,media-controller" property with a change of compatible string. Signed-off-by: Dave Stevenson <[email protected]>

Add the downstream Unicam driver back into all builds as VIDEO_BCM2835_UNICAM_LEGACY (VIDEO_BCM2835_UNICAM is the upstream Unicam driver) Signed-off-by: Dave Stevenson <[email protected]>

The upstream Unicam driver needs a set of userland changes to get libcamera to run, and those aren't written or merged yet. Move the "brcm,bcm2835-unicam" compatible from the upstream driver to the old downstream version so that users can run libcamera against 6.10. Once the libcamera changes have been merged this can be reverted to use the upstream driver. If using the non-legacy compatible then assume we want to use media-controller API for configuration. Signed-off-by: Dave Stevenson <[email protected]>

Automatic link power saving plus the ability of a root complex to buffer pending posted write transfers (and consider them complete before being transmitted on the wire) causes compression of updates to GPIO state. The large bandwidth of a Gen 2 x4 link means the writes toggle state inside RP1 as fast as it can go (~20MHz), which is bad for applications wanting bitbash with at least a few microseconds of delay between updates. By tailoring IO access patterns to a special Root Complex register, writes to GPIOs can be stalled until the link wakes - meaning all writes end up with a reasonably consistent minimum pacing (~200ns). Additionally, write barriers have no effect other than to arbitrarily delay some writes by a small, variable amount - so remove the vast majority of these in areas that could be hot-paths. Although the IO memory is mapped with Device strongly-ordered semantics, this doesn't prevent the splitter inside BCM2712 from letting an MMIO read request to a GPIO register get ahead of the pacing writes to the Root Complex register. So each pin state read must flush writes out to the Outer-Shareable domain. Signed-off-by: Jonathan Bell <[email protected]>

Video encode can defer generating the header until the first frame is presented, which allows it to take the colourspace information from the frame rather than just the format. Enable that for the V4L2 driver now that the firmware populates all the parameters. raspberrypi/firmware#1885 Signed-off-by: Dave Stevenson <[email protected]>

We do NOT claim to support decoding in real-time for these levels, but can transcode some content, and handle 1920x1200. Signed-off-by: Dave Stevenson <[email protected]>

TMOD_TO is the transmit-only mode that doesn't put data into the receive FIFO. Using TMOD_TO when the user doesn't want the received data saves CPU time and memory bandwidth. Signed-off-by: Phil Elwell <[email protected]>

TMOD_RO is the receive-only mode that doesn't require data in the transmit FIFO in order to generate clock cycles. Using TMOD_RO when the device doesn't care about the data sent to it saves CPU time and memory bandwidth. Signed-off-by: Phil Elwell <[email protected]>

Disabling the peripheral resets controller state which has a dangerous side-effect of disabling the DMA handshake interface while it is active. This can cause DMA channels to hang. The error recovery pathway will wait for DMA to stop and reset the chip anyway, so mask further FIFO interrupts and let the transfer finish gracefully. Signed-off-by: Jonathan Bell <[email protected]>

Channels 1-2 have a statically configured maximum MSIZE of 8, and channels 3-8 have MSIZE set to 4. The DMAC "helpfully" silently truncates bursts to the hardware supported maximum, so any FIFO read operation with an oversized burst threshold will leave a residue of threshold minus MSIZE rows. As channel allocation is dynamic, this means every client needs to use a maximum of 4 for burst length. AXI AWLEN/ARLEN constraints aren't strictly related to MSIZE, except that bursts won't be issued that are longer than MSIZE beats. Therefore, it's a useful proxy to tell clients of the DMAC the hardware limitations. Signed-off-by: Jonathan Bell <[email protected]>

There's no real need to constrain MEM access widths to 32-bit (or narrower), as the DMAC is intelligent enough to size memory accesses appropriately. Wider accesses are more efficient. Similarly, MEM burst lengths don't need to be a function of DEV burst lengths - the DMAC packs/unpacks data into/from its internal channel FIFOs appropriately. Longer accesses are more efficient. However, the DMAC doesn't have complete support for unaligned accesses, and blocks are always defined in integer multiples of SRC_WIDTH, so odd source lengths or buffer alignments will prevent wide accesses being used, as before. There is an implicit requirement to limit requested DEV read burst lengths to less than the hardware's maximum configured MSIZE - otherwise RX data will be left over at the end of a block. There is no config register that reports this value, so the AXI burst length parameter is used to produce a facsimile of it. Warn if such a request arrives that doesn't respect this. Signed-off-by: Jonathan Bell <[email protected]>

This issue was due to a misconfiguration of the RP1 DMAC due to hardware limitations, not the SPI driver (which was using the incorrect reported maximum burst size to set the FIFO threshold). This reverts commit 6aab06f. Signed-off-by: Jonathan Bell <[email protected]>

If the associated DMA controller has lower burst length support than the level the FIFO is set to, then bytes will be left in the RX FIFO at the end of a DMA block - requiring a round-trip through the timeout interrupt handler rather than an end-of-block DMA interrupt. Signed-off-by: Jonathan Bell <[email protected]>

Do an end-run around ASoC in lieu of not being able to easily find the associated DMA controller capabilities. Signed-off-by: Jonathan Bell <[email protected]>

…ints Valid ranges for the I2S peripheral's FIFO configuration include a depth of 16 - unconditionally setting the burst length to 16 with a fifo threshold of size/2 will cause under/overflows. For DMA engines with restricted capabilities the requested burst length and FIFO thresholds need to be adjusted downward accordingly. Both the RX and TX FIFOs operate on "less-than" thresholds. Setting the TX threshold to fifo_size minus burst means the FIFO is kept nearly-full. Signed-off-by: Jonathan Bell <[email protected]>

The associated DMAC has channels that do not support longer bursts. Signed-off-by: Jonathan Bell <[email protected]>

Whilst BCM2712 does fix using odd horizontal timings, it doesn't work with interlaced modes. Drop the workaround for interlaced modes and revert to the same behaviour as BCM2711. raspberrypi#6281 Signed-off-by: Dave Stevenson <[email protected]>

This produces a hard fail on later (6.11) kernels. See: https://lore.kernel.org/all/[email protected]/ Signed-off-by: Dom Cobley <[email protected]>

Ensure the transmit FIFO has emptied before ending the transfer by dropping the TX threshold to 0 when the last byte has been pushed into the FIFO. Include a similar fix for the non-IRQ paths. See: raspberrypi#6285 Fixes: 6014649 ("spi: dw: Save bandwidth with the TMOD_TO feature") Signed-off-by: Phil Elwell <[email protected]>

The DW SPI interface has a 16-bit clock divider, where the bottom bit of the divisor must be 0. Limit how low the clock speed can go to prevent the clock divider from being truncated, as that could lead to a much higher clock rate than requested. Signed-off-by: Phil Elwell <[email protected]>

Signed-off-by: Phil Elwell <[email protected]>

There is now an ssd1327-spi overlay, but it's of little use without the corresponding display drivers. Add them as modules to the usual defconfig files. Signed-off-by: Phil Elwell <[email protected]>

Using the "cores * 1.5" heuristic, configure the kernel builds for the 4-core GitHub-hosted runners. Signed-off-by: Phil Elwell <[email protected]>

The DT property for the BQ32000 controlled by trickle-resistor-ohms parameter should be "trickle-resistor-ohms", not "abracon,tc-resistor". See: raspberrypi#6291 Signed-off-by: Phil Elwell <[email protected]>

Many HD44780 LCD displays are connected via very common I2C GPIO expander. We have an overlay for connecting the displays directly to GPIOs, but not one for it connected via a backpack. Add such an overlay. Signed-off-by: Dave Stevenson <[email protected]>

The default values defining a 16x2 display weren't documented, so add them. Signed-off-by: Dave Stevenson <[email protected]>

The corresponding driver implementation has seen sufficient testing, so enable by default. Retain the dtparam so it can be turned off for test. Signed-off-by: Jonathan Bell <[email protected]>

In the same way that other subsystems support the setting of device id numbers from Device Tree aliases, allow gpiochip numbers to be derived from "gpiochip<n>" aliases. Signed-off-by: Phil Elwell <[email protected]>

Add a gpiochip0 aliase pointing to the rp1 GPIO node, making it appear as gpiochip0. Signed-off-by: Phil Elwell <[email protected]>

Make the BCM2712's onboard GPIOs start at gpiochip10, marking them out as system resources and preventing accidental use by existing Pi 5 code. Signed-off-by: Phil Elwell <[email protected]>

Allow block devices to be used as caches for other devices. The primary use is to allow small, low latency media to act as caches for spinning rust drives. See: raspberrypi#6303 raspberrypi#455 Signed-off-by: Phil Elwell <[email protected]>

Add CONFIG_ZRAM_WRITEBACK=y and CONFIG_ZRAM_MULTI_COMP=y. See: raspberrypi#2939 Signed-off-by: Phil Elwell <[email protected]>

This reverts commit abb1ad6. See: raspberrypi#6294 Signed-off-by: Phil Elwell <[email protected]>

This patch adds definitions related to the Branch Record Buffer Extension (BRBE) as per ARM DDI 0487K.a. These will be used by KVM and a BRBE driver in subsequent patches. Some existing BRBE definitions in asm/sysreg.h are replaced with equivalent generated definitions. Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Cc: Marc Zyngier <[email protected]> Cc: Mark Rutland <[email protected]> Cc: [email protected] Cc: [email protected] Reviewed-by: Mark Rutland <[email protected]> Reviewed-by: Mark Brown <[email protected]> Signed-off-by: Anshuman Khandual <[email protected]> ---- Changes in V18: - Changed BRBIDR0_EL1 register fields CC and FORMAT, updated the commit message arch/arm64/include/asm/sysreg.h | 17 ++--- arch/arm64/tools/sysreg | 131 ++++++++++++++++++++++++++++++++ 2 files changed, 137 insertions(+), 11 deletions(-)

The Branch Record Buffer Extension (BRBE) adds a number of system registers and instructions, which we don't currently intend to expose to guests. Our existing logic handles this safely, but this could be improved with some explicit handling of BRBE. The presence of BRBE is currently hidden from guests as the cpufeature code's ftr_id_aa64dfr0[] table doesn't have an entry for the BRBE field, and so this will be zero in the sanitised value of ID_AA64DFR0 exposed to guests via read_sanitised_id_aa64dfr0_el1(). As the ftr_id_aa64dfr0[] table may gain an entry for the BRBE field in future, for robustness we should explicitly mask out the BRBE field in read_sanitised_id_aa64dfr0_el1(). The BRBE system registers and instructions are currently trapped by the existing configuration of the fine-grained traps. As neither the registers nor the instructions are described in the sys_reg_descs[] table, emulate_sys_reg() will warn that these are unknown before injecting an UNDEFINED exception into the guest. Well-behaved guests shouldn't try to use the registers or instructions, but badly-behaved guests could use these, resulting in unnecessary warnings. To avoid those warnings, we should explicitly handle the BRBE registers and instructions as UNDEFINED. Address the above by having read_sanitised_id_aa64dfr0_el1() mask out the ID_AA64DFR0.BRBE field, and explicitly handling all of the BRBE system registers and instructions as UNDEFINED. Cc: Marc Zyngier <[email protected]> Cc: Oliver Upton <[email protected]> Cc: James Morse <[email protected]> Cc: Suzuki K Poulose <[email protected]> Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Anshuman Khandual <[email protected]> ---- Changes in V18: - Updated the commit message arch/arm64/kvm/sys_regs.c | 56 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) Reviewed-by: Mark Rutland <[email protected]> Reviewed-by: Mark Rutland <[email protected]>

In order to support the Branch Record Buffer Extension (BRBE), we need to extend the arm_pmu framework with some basic infrastructure for branch stack sampling which arm_pmu drivers can opt-in to using. Subsequent patches will use this to add support for BRBE in the PMUv3 driver. With BRBE, the hardware records branches into a hardware FIFO, which will be sampled by software when perf events overflow. A task may be context- switched an arbitrary number of times between overflows, and to avoid losing samples we need to save the current records when a task is context- switched out. To do these we'll need to use the pmu::sched_task() callback, and we'll also need to allocate some per-task storage space via event flag PERF_ATTACH_TASK_DATA. Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Cc: Mark Rutland <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Anshuman Khandual <[email protected]> ---- Changes in V18: - Scan valid branch stack events in armpmu_start() to create merged filter - Updated the commit message drivers/perf/arm_pmu.c | 42 +++++++++++++++++++++++++++++++++--- include/linux/perf/arm_pmu.h | 32 ++++++++++++++++++++++++++- 2 files changed, 70 insertions(+), 4 deletions(-)

Fine grained trap control for BRBE registers, and instructions access need to be configured in HDFGRTR_EL2, HDFGWTR_EL2 and HFGITR_EL2 registers when kernel enters at EL1 but EL2 is present. This changes __init_el2_fgt() as required. Similarly cycle and mis-prediction capture need to be enabled in BRBCR_EL1 and BRBCR_EL2 when the kernel enters either into EL1 or EL2. This adds new __init_el2_brbe() to achieve this objective. This also updates Documentation/arch/arm64/booting.rst with all the above EL2 along with MDRC_EL3.SBRBE requirements. First this replaces an existing hard encoding (1 << 62) with corresponding applicable macro HDFGRTR_EL2_nPMSNEVFR_EL1_MASK. Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Cc: Jonathan Corbet <[email protected]> Cc: Marc Zyngier <[email protected]> Cc: Oliver Upton <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Anshuman Khandual <[email protected]> ---- Changes in V18: - Dropped ifdef CONFIG_ARM64_BRBE around __init_el2_brbe() - Updated the in code comment around __init_el2_brbe() - Dropped the write up for EL2->EL1 transition, moved up the EL3 write up Documentation/arch/arm64/booting.rst | 21 +++++++ arch/arm64/include/asm/el2_setup.h | 87 +++++++++++++++++++++++++++- 2 files changed, 105 insertions(+), 3 deletions(-)

This extends recently added branch stack sampling framework in ARMV8 PMU to enable such events via new architecture feature called Branch Record Buffer Extension aka BRBE. This implements all the armv8pmu_branch_xxx() callbacks as expected at ARMV8 PMU level required to drive perf branch stack sampling events. This adds a new config option CONFIG_ARM64_BRBE to encapsulate this BRBE based implementation, available only on ARM64 platforms. BRBE hardware captures a branch record via three distinct system registers representing branch source address, branch target address, and other branch information. A BRBE buffer implementation is organized as multiple banks of 32 branch records each, which is a collection of BRBSRC_EL1, BRBTGT_EL1 and BRBINF_EL1 registers. Though total BRBE record entries i.e BRBE_MAX_ENTRIES cannot exceed MAX_BRANCH_RECORDS as defined for ARM PMU. Branch stack sampling is enabled and disabled along with regular PMU events . This adds required function callbacks in armv8pmu_branch_xxx() format, to drive the PMU branch stack hardware when supported. This also adds fallback stub definitions for these callbacks for PMUs which would not have required support. BRBE hardware attributes get captured in a new reg_brbidr element in struct arm_pmu during armv8pmu_branch_probe() which is called from broader probing function __armv8pmu_probe_pmu(). Attributes such as number of branch record entries implemented in the hardware can be derived from armpmu->reg_brbidr. BRBE gets enabled via armv8pmu_branch_enable() where it also derives branch filter, and additional requirements from event's 'attr.branch_sample_type' and configures them via BRBFCR_EL1 and BRBCR_EL1 registers. PMU event overflow triggers IRQ, where current branch records get captured, stitched along with older records available in 'task_ctx', before getting processed for core perf ring buffer. Task context switch outs incrementally save current branch records in event's 'pmu_ctx->task_ctx_data' to optimize workload's branch record samples. In case multiple events with different branch sample type requests converge on the same PMU, BRBE gets enabled for the merged branch filter accommoding all those event's branch sample type. Captured branch records get filterted in software for an overflown event if BRBE hardware config does not match its branch sample type, while handling the PMU IRQ. Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Cc: Mark Rutland <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Anshuman Khandual <[email protected]> ---- Changes in V18: - Replaced BRBIDR0_EL1_FORMAT_0 as BRBIDR0_EL1_FORMAT_FORMAT_0 in BRBE driver - Added SW filtering framework in read_branch_records() during filter mismatch - Added SW filtering for both privilege modes and branch types drivers/perf/Kconfig | 11 + drivers/perf/Makefile | 1 + drivers/perf/arm_brbe.c | 1198 +++++++++++++++++++++++++++++++ drivers/perf/arm_pmuv3.c | 160 ++++- drivers/perf/arm_pmuv3_branch.h | 83 +++ include/linux/perf/arm_pmu.h | 5 + 6 files changed, 1457 insertions(+), 1 deletion(-) create mode 100644 drivers/perf/arm_brbe.c create mode 100644 drivers/perf/arm_pmuv3_branch.h

Disable the BRBE before we enter the guest, saving the status and enable it back once we get out of the guest. This avoids capturing branch records in the guest kernel or userspace, which would be confusing the host samples. Cc: Marc Zyngier <[email protected]> Cc: Oliver Upton <[email protected]> Cc: James Morse <[email protected]> Cc: Suzuki K Poulose <[email protected]> Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Cc: [email protected] Cc: [email protected] CC: [email protected] Signed-off-by: Anshuman Khandual <[email protected]> ---- Changes in V18: - Used host_data_ptr() to access host_debug_state.brbcr_el1 register - Changed DEBUG_STATE_SAVE_BRBE to use BIT(7) - Reverted back iflags as u8 arch/arm64/include/asm/kvm_host.h | 3 +++ arch/arm64/kvm/debug.c | 5 +++++ arch/arm64/kvm/hyp/nvhe/debug-sr.c | 31 ++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+)

The test runs quite slowly in the model, so replace "xargs -n1" with "tr ' ' '\n'" which does the same thing but in single digit minutes instead of double digit minutes. Also reduce the number of loops in the test application. Unfortunately this causes intermittent failures on x86, presumably because the sampling interval is too big to pickup any loops, so keep it the same there. Cc: Mark Rutland <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: James Clark <[email protected]> Signed-off-by: Anshuman Khandual <[email protected]>

In the perf script command, spaces are turned into newlines. But when there is a double space this results in empty lines which fail the following inverse grep test, so strip the empty lines. Cc: Mark Rutland <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: James Clark <[email protected]> Signed-off-by: Anshuman Khandual <[email protected]>

Add Arm64 BRBE-specific testing to the existing branch stack sampling test. The test currently passes on the Arm FVP RevC model, but no hardware has been tested yet. Cc: Mark Rutland <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: [email protected] Cc: [email protected] Co-developed-by: German Gomez <[email protected]> Signed-off-by: German Gomez <[email protected]> Signed-off-by: James Clark <[email protected]> Signed-off-by: Anshuman Khandual <[email protected]>

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TEST: Perf branch stack sampling #6330

TEST: Perf branch stack sampling #6330

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TEST: Perf branch stack sampling #6330

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TEST: Perf branch stack sampling #6330

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