An analysis of 2 alternative solutions

Table of contents

• A recall to the project objectives
• Potential solutions
  • Proposal 1: Full external implementation
  • Proposal 2: Implementation integrated in the chisel compilation pipeline
• Conclusion

A recall to the project objectives

In order to display waveforms of a Chisel circuit while preserving source code "representation" the project should:

1. collect high-level debug information (DI) of a circuit;
2. elaborate the DI in order to associate it with the values in a trace from a simulator, in other words an association with the signals and modules output of a chisel-CIRCT compilation;
3. emit a well-defined file format that a viewer can read together with a trace file to properly display the waveforms;
4. make everything compatible and portable with the new ChiselSim.

Potential solutions

In order to realize it, two alternative solutions of different nature have been proposed:

• one providing a unique library external to chisel
• the other one integrated in the chisel compilation pipeline itself

Proposal 1: Full external implementation

The former would need to parse all the intermediate representations (IRs) used, like "Chisel IR" and "FIRRTL IR", and the debug info already emitted by the firtool compiler (the HGLDD file), then join the signals of the IRs together by identifying IDs based on some "fixed" value and finally emitting a file (like a symbol table) for the viewer. However, considering that the IRs used are part of a private package in the chisel library and subject to potential changes, there is no opportunity to guarantee a unique ID for each signal and the maintainability over years would be even more difficult. Because of that, an implementation following this approach would be too complex and less reliable. For more information please refer to the drawbacks section in the "old approach".

Reference: https://github.com/rameloni/tywaves-chisel-demo/wiki/An-alternative-solution-(old-demo-version)

Proposal 2: Implementation integrated in the chisel compilation pipeline

Thus, an integrated solution reveals as the best choice. It would solve the problem of the unique ID and, at the same time, it can improve the maintainability. The idea is to generate the information directly when the transformation from one IR to another is done, namely, between the "Chisel IR" and "FIRRTL IR" in the chisel library, pass this information to the firtool and emit the file for the viewer directly from there, either next to or within the existing HGLDD.

Conclusion

As a consequence of its disadvantages, the first proposal revealed not ideal, therefore, the second approach has been chosen for this project. The rest of this wiki shows details of its actual implementation.