Use sysctls available in macOS 12/iOS 15 for Apple silicon

[Developer-Ecosystem-Engineering]

The patch applies to ARM and should not change any behavior for x86_64 / Intel. In general, it'll use newer sysctls when they're available, but fallback to previous implementations when they're not present. Newer sysctls are available in iOS 15 and macOS Monterey 12.

• Added FHM ARM ISA feature
• Added support for Apple chips to have different cache configurations for the different core types in the same package
• Updated cache-info to print various cache configurations if multiple are present
• Updated package.name to also query machdep.cpu.brand_string if decode of hw.machine fails
• Updated README.md to include macOS ARM64 support

Example output:

Previous cpu-info running on macOS / M1:

Packages:
        0:
Microarchitectures:
        4x Firestorm
        4x Icestorm
Cores:
        0: 1 processor (0), Apple Firestorm
        1: 1 processor (1), Apple Firestorm
        2: 1 processor (2), Apple Firestorm
        3: 1 processor (3), Apple Firestorm
        4: 1 processor (4), Apple Icestorm
        5: 1 processor (5), Apple Icestorm
        6: 1 processor (6), Apple Icestorm
        7: 1 processor (7), Apple Icestorm
Logical processors:
        0
        1
        2
        3
        4
        5
        6
        7

cpu-info running on macOS / M1 after patch:

Packages:
        0: Apple M1
Microarchitectures:
        4x Firestorm
        4x Icestorm
Cores:
        0: 1 processor (0), Apple Firestorm
        1: 1 processor (1), Apple Firestorm
        2: 1 processor (2), Apple Firestorm
        3: 1 processor (3), Apple Firestorm
        4: 1 processor (4), Apple Icestorm
        5: 1 processor (5), Apple Icestorm
        6: 1 processor (6), Apple Icestorm
        7: 1 processor (7), Apple Icestorm
Logical processors:
        0
        1
        2
        3
        4
        5
        6
        7

Previous isa-info running on macOS / M1:

Instruction sets:
        ARM v8.1 atomics: yes
        ARM v8.1 SQRDMLxH: no
        ARM v8.2 FP16 arithmetics: yes
        ARM v8.3 dot product: yes
        ARM v8.3 JS conversion: no
        ARM v8.3 complex: no
SIMD extensions:
        ARM SVE: no
        ARM SVE 2: no
Cryptography extensions:
        AES: yes
        SHA1: yes
        SHA2: yes
        PMULL: yes
        CRC32: yes

isa-info running on macOS Monterey 12 / M1 after patch:

Instruction sets:
        ARM v8.1 atomics: yes
        ARM v8.1 SQRDMLxH: yes
        ARM v8.2 FP16 arithmetics: yes
        ARM v8.2 FHM: yes
        ARM v8.3 dot product: yes
        ARM v8.3 JS conversion: yes
        ARM v8.3 complex: yes
SIMD extensions:
        ARM SVE: no
        ARM SVE 2: no
Cryptography extensions:
        AES: yes
        SHA1: yes
        SHA2: yes
        PMULL: yes
        CRC32: yes

Previous cache-info running on macOS / M1:

Max cache size (upper bound): 4194304 bytes
L1 instruction cache: 8 x 128 KB, 4-way set associative (256 sets), 128 byte lines, shared by 1 processors
L1 data cache: 8 x 64 KB, 4-way set associative (128 sets), 128 byte lines, shared by 1 processors
L2 data cache: 4 MB (exclusive), 8-way set associative (4096 sets), 128 byte lines, shared by 8 processors

cache-info running on macOS Monterey 12 / M1 after patch:

Max cache size (upper bound): 12582912 bytes
L1 instruction cache: 4 x 192 KB, 4-way set associative (384 sets), 128 byte lines, shared by 1 processors
L1 instruction cache: 4 x 128 KB, 4-way set associative (256 sets), 128 byte lines, shared by 1 processors
L1 data cache: 4 x 128 KB, 4-way set associative (256 sets), 128 byte lines, shared by 1 processors
L1 data cache: 4 x 64 KB, 4-way set associative (128 sets), 128 byte lines, shared by 1 processors
L2 data cache: 12 MB (exclusive), 8-way set associative (12288 sets), 128 byte lines, shared by 4 processors
L2 data cache: 4 MB (exclusive), 8-way set associative (4096 sets), 128 byte lines, shared by 4 processors

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[malfet]

Closing as duplicated in #96

[dlenski]

The description of this PR mentions:

Updated package.name to also query machdep.cpu.brand_string if decode of hw.machine fails

But then that functionality was omitted (inadvertently?) in its refactoring in #100. I've added it back in #246.