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Fix SV lint.
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Yvan Tortorella committed Feb 17, 2024
1 parent 5b2de20 commit 72e1fa7
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Showing 16 changed files with 246 additions and 204 deletions.
16 changes: 8 additions & 8 deletions rtl/redmule_castin.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ import redmule_pkg::*;
module redmule_castin #(
parameter fpnew_pkg::fmt_logic_t FpFmtConfig = FpFmtConfig,
parameter fpnew_pkg::ifmt_logic_t IntFmtConfig = IntFmtConfig,
parameter fpnew_pkg::fp_format_e dst_format = FPFORMAT,
parameter fpnew_pkg::fp_format_e DstFormat = FPFORMAT,
parameter fpnew_pkg::operation_e Operation = CAST_OP,
parameter logic Pipe = 1'b0 ,
localparam int unsigned BW = hci_package::DEFAULT_BW ,
Expand Down Expand Up @@ -47,10 +47,10 @@ logic [NUM_CAST-1:0][WIDTH-1:0] result ,
operand;

generate
for (genvar i = 0; i < NUM_CAST; i++) begin : generate_cast_units
for (genvar i = 0; i < NUM_CAST; i++) begin : gen_cast_units

assign operand [i] = {{ZEROBITS{1'b0}}, src_int[i*MIN_FMT+:MIN_FMT]};

fpnew_cast_multi #(
.FpFmtConfig ( FpFmtConfig ),
.IntFmtConfig ( IntFmtConfig )
Expand All @@ -63,7 +63,7 @@ generate
.op_i ( Operation ),
.op_mod_i ( '0 ),
.src_fmt_i ( src_fmt_i ),
.dst_fmt_i ( dst_format ),
.dst_fmt_i ( DstFormat ),
.int_fmt_i ( INT_SRC ),
.tag_i ( '0 ),
.mask_i ( '0 ),
Expand All @@ -81,11 +81,11 @@ generate
.out_ready_i ( '1 ),
.busy_o ( )
);

assign dst_int [i*WIDTH+:WIDTH] = result[i];
end // block: generate_cast_units

end

endgenerate

assign dst_o = cast_i ? dst_int : src_i;
Expand Down
12 changes: 6 additions & 6 deletions rtl/redmule_castout.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ import redmule_pkg::*;
module redmule_castout #(
parameter fpnew_pkg::fmt_logic_t FpFmtConfig = FpFmtConfig,
parameter fpnew_pkg::ifmt_logic_t IntFmtConfig = IntFmtConfig,
parameter fpnew_pkg::fp_format_e src_format = FPFORMAT,
parameter fpnew_pkg::fp_format_e SrcFormat = FPFORMAT,
parameter fpnew_pkg::operation_e Operation = CAST_OP,
parameter logic Pipe = 1'b0 ,
localparam int unsigned BW = hci_package::DEFAULT_BW ,
Expand Down Expand Up @@ -43,7 +43,7 @@ logic [NUM_CAST-1:0][WIDTH-1:0] result ,
operand;

generate
for (genvar i = 0; i < NUM_CAST; i++) begin : generate_cast_units
for (genvar i = 0; i < NUM_CAST; i++) begin : gen_cast_units

assign operand [i] = src_i[i*WIDTH+:WIDTH];

Check warning on line 49 in rtl/redmule_castout.sv

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] rtl/redmule_castout.sv#L49 

Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output 
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]"  location:{path:"rtl/redmule_castout.sv"  range:{start:{line:49  column:1}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}  suggestions:{range:{start:{line:49  column:1}  end:{line:50}}  text:"\n"}
Expand All @@ -58,7 +58,7 @@ generate
.rnd_mode_i ( fpnew_pkg::RNE ),
.op_i ( Operation ),
.op_mod_i ( '0 ),
.src_fmt_i ( src_format ),
.src_fmt_i ( SrcFormat ),
.dst_fmt_i ( dst_fmt_i ),
.int_fmt_i ( INT_SRC ),
.tag_i ( '0 ),
Expand All @@ -77,11 +77,11 @@ generate
.out_ready_i ( '1 ),
.busy_o ( )
);

assign res [i*MIN_FMT+:MIN_FMT] = result[i][WIDTH-MIN_FMT-1:0];

end

endgenerate

assign dst_int = {{DATA_W-DW_CUT{1'b0}}, res[DATA_W-DW_CUT-1:0]};
Expand Down
2 changes: 1 addition & 1 deletion rtl/redmule_ce.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -73,7 +73,7 @@ cluster_clock_gating stage2_noncomp_clk_gating (

logic [NumPipeRegs-1:0][BITW-1:0] noncomp_y_q;
generate
for (genvar i = 0; i < NumPipeRegs; i++) begin : noncomp_input_pipe
for (genvar i = 0; i < NumPipeRegs; i++) begin : gen_noncomp_input_pipe
always_ff @(posedge stage2_noncomp_input_pipe_clk, negedge rst_ni) begin
if (~rst_ni) begin
noncomp_y_q[i] <= '0;
Expand Down
57 changes: 33 additions & 24 deletions rtl/redmule_complex.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -15,35 +15,42 @@ module redmule_complex
import hwpe_ctrl_package::*;
import hwpe_stream_package::*;
#(
parameter core_type_e CoreType = CV32X , // CV32E40P, IBEX, SNITCH, CVA6
parameter int unsigned ID_WIDTH = 8 ,
parameter int unsigned N_CORES = 8 ,
parameter int unsigned DW = DATA_W , // TCDM port dimension (in bits)
parameter int unsigned MP = DW/redmule_pkg::MemDw,
parameter int unsigned NumIrqs = 32 ,
parameter int unsigned AddrWidth = 32 ,
parameter int unsigned XPulp = 0 ,
parameter int unsigned FpuPresent = 0 ,
parameter int unsigned Zfinx = 0 ,
parameter type core_data_req_t = logic ,
parameter type core_data_rsp_t = logic ,
parameter type core_inst_req_t = logic ,
parameter type core_inst_rsp_t = logic ,
parameter type redmule_data_req_t = logic ,
parameter type redmule_data_rsp_t = logic ,
localparam fp_format_e FpFormat = FPFORMAT , // Data format (default is FP16)
localparam int unsigned Height = ARRAY_HEIGHT , // Number of PEs within a row
localparam int unsigned Width = ARRAY_WIDTH , // Number of parallel rows
localparam int unsigned NumPipeRegs = PIPE_REGS , // Number of pipeline registers within each PE
localparam pipe_config_t PipeConfig = DISTRIBUTED ,
localparam int unsigned BITW = fp_width(FpFormat) // Number of bits for the given format
// CV32E40P, IBEX, SNITCH, CVA6
parameter core_type_e CoreType = CV32X,
parameter int unsigned ID_WIDTH = 8,
parameter int unsigned N_CORES = 8,
// TCDM port dimension (in bits)
parameter int unsigned DW = DATA_W,
parameter int unsigned MP = DW/redmule_pkg::MemDw,
parameter int unsigned NumIrqs = 32,
parameter int unsigned AddrWidth = 32,
parameter int unsigned XPulp = 0,
parameter int unsigned FpuPresent = 0,
parameter int unsigned Zfinx = 0,
parameter type core_data_req_t = logic,
parameter type core_data_rsp_t = logic,
parameter type core_inst_req_t = logic,
parameter type core_inst_rsp_t = logic,
parameter type redmule_data_req_t = logic,
parameter type redmule_data_rsp_t = logic,
// Data format (default is FP16)
localparam fp_format_e FpFormat = FPFORMAT,
// Number of PEs within a row
localparam int unsigned Height = ARRAY_HEIGHT,
// Number of parallel rows
localparam int unsigned Width = ARRAY_WIDTH,
// Number of pipeline registers within each PE
localparam int unsigned NumPipeRegs = PIPE_REGS,
localparam pipe_config_t PipeConfig = DISTRIBUTED,
// Number of bits for the given format
localparam int unsigned BITW = fp_width(FpFormat)
)(
input logic clk_i ,
input logic rst_ni ,
input logic test_mode_i ,
input logic fetch_enable_i ,
input logic [ AddrWidth-1:0] boot_addr_i ,
input logic [ NumIrqs-1:0] irq_i ,
input logic [ AddrWidth-1:0] boot_addr_i ,
input logic [ NumIrqs-1:0] irq_i ,
output logic [$clog2(NumIrqs)-1:0] irq_id_o ,
output logic irq_ack_o ,
output logic core_sleep_o ,
Expand All @@ -62,8 +69,10 @@ logic busy;
logic s_clk, s_clk_en;
logic [N_CORES-1:0][1:0] evt;

// verilog_lint: waive-start line-length
`HWPE_CTRL_TYPEDEF_REQ_T(redmule_ctrl_req_t, logic [31:0], logic [31:0], logic [3:0], logic [ID_WIDTH-1:0])
`HWPE_CTRL_TYPEDEF_RSP_T(redmule_ctrl_rsp_t, logic [31:0], logic [ID_WIDTH-1:0])
// verilog_lint: waive-stop line-length

core_inst_req_t core_inst_req;
core_inst_rsp_t core_inst_rsp;
Expand Down
64 changes: 36 additions & 28 deletions rtl/redmule_ctrl.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -10,17 +10,17 @@ import redmule_pkg::*;
module redmule_ctrl
import hwpe_ctrl_package::*;
#(
parameter int unsigned N_CORES = 8 ,
parameter int unsigned IO_REGS = REDMULE_REGS ,
parameter int unsigned ID_WIDTH = 8 ,
parameter int unsigned SysDataWidth = 32 ,
parameter int unsigned N_CONTEXT = 2 ,
parameter int unsigned Height = 4 ,
parameter int unsigned Width = 8 ,
parameter int unsigned NumPipeRegs = 3 ,
localparam int unsigned TILE = (NumPipeRegs +1)*Height,
localparam int unsigned W_ITERS = W_ITERS ,
localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
parameter int unsigned N_CORES = 8 ,
parameter int unsigned IO_REGS = REDMULE_REGS ,
parameter int unsigned ID_WIDTH = 8 ,
parameter int unsigned SysDataWidth = 32 ,
parameter int unsigned N_CONTEXT = 2 ,
parameter int unsigned Height = 4 ,
parameter int unsigned Width = 8 ,
parameter int unsigned NumPipeRegs = 3 ,
localparam int unsigned TILE = (NumPipeRegs +1)*Height,
localparam int unsigned W_ITERS = W_ITERS ,
localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
)(
input logic clk_i ,
input logic rst_ni ,
Expand Down Expand Up @@ -62,8 +62,16 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
logic [15:0] w_rows_iter, w_row_count_d, w_row_count_q;
logic [15:0] z_storings_d, z_storings_q, tot_stores, issued_store_d, issued_store_q;

typedef enum logic [2:0] {REDMULE_IDLE, REDMULE_STARTING, REDMULE_COMPUTING, REDMULE_BUFFERING, REDMULE_STORING, REDMULE_FINISHED} redmule_ctrl_state;
redmule_ctrl_state current, next;
typedef enum logic [2:0] {
REDMULE_IDLE,
REDMULE_STARTING,
REDMULE_COMPUTING,
REDMULE_BUFFERING,
REDMULE_STORING,
REDMULE_FINISHED
} redmule_ctrl_state_e;

redmule_ctrl_state_e current, next;

hwpe_ctrl_package::ctrl_regfile_t reg_file_d, reg_file_q;
hwpe_ctrl_package::ctrl_slave_t cntrl_slave;
Expand Down Expand Up @@ -109,7 +117,7 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
if(~rst_ni) begin
current <= REDMULE_IDLE;
end else begin
if (clear)
if (clear)
current <= REDMULE_IDLE;
else
current <= next;
Expand All @@ -121,14 +129,14 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
if(~rst_ni) begin
w_row_count_q <= '0;
end else begin
if (clear)
if (clear)
w_row_count_q <= '0;
else
w_row_count_q <= w_row_count_d;
end
end

always_ff @(posedge clk_i or negedge rst_ni) begin
always_ff @(posedge clk_i or negedge rst_ni) begin
if(~rst_ni) begin
count_w_q <= 1'b0;
end else begin
Expand Down Expand Up @@ -195,7 +203,7 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
end else begin
if (last_w_row_rst || clear)
last_w_row <= 1'b0;
else if (last_w_row_en)
else if (last_w_row_en)
last_w_row <= 1'b1;
end
end
Expand All @@ -219,7 +227,7 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
if(~rst_ni) begin
z_storings_q <= '0;
end else begin
if (clear || storing_rst)
if (clear || storing_rst)
z_storings_q <= '0;
else
z_storings_q <= z_storings_d;
Expand Down Expand Up @@ -249,7 +257,7 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
/*---------------------------------------------------------------------------------------------*/
/* Controller FSM */
/*---------------------------------------------------------------------------------------------*/
// This is a local FSM who's only work is to make the first
// This is a local FSM who's only work is to make the first
// input load operation and to start the redmule_scheduler
always_comb begin : controller_fsm
tiler_setback = 1'b0;
Expand Down Expand Up @@ -290,10 +298,10 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
finish_d = 1'b0;
next = REDMULE_STARTING;
end
else
else
next = REDMULE_IDLE;
end

REDMULE_STARTING: begin
w_shift_o = 1'b0;
cntrl_scheduler_o.first_load = 1'b1;
Expand All @@ -307,7 +315,7 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
REDMULE_COMPUTING: begin
if (w_loaded_i)
w_row_count_d = w_row_count_q + 1;

if (w_row_count_d == Height && !count_w_q)
w_computed_en = 1'b1;
else if (w_row_count_q == w_rows_iter) begin
Expand All @@ -316,7 +324,7 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
if (!last_w_row)
last_w_row_en = 1'b1;
end

case (last_w_row)
1'b0: begin
if (w_computed == NumPipeRegs) begin
Expand All @@ -343,7 +351,7 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
end
endcase
end

REDMULE_BUFFERING: begin
z_buffer_clk_en = 1'b1;
if (last_w_row)
Expand All @@ -358,10 +366,10 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
else
next = REDMULE_BUFFERING;
end

REDMULE_STORING: begin
cntrl_scheduler_o.storing = 1'b1;

if (w_loaded_i)
w_row_count_d = w_row_count_q + 1;

Expand All @@ -377,7 +385,7 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
end
end
end

REDMULE_FINISHED: begin
cntrl_slave.done = 1'b1;
busy_o = 1'b0;
Expand All @@ -399,6 +407,6 @@ localparam int unsigned LEFT_PARAMS = LEFT_PARAMS
/* Other combinational assigmnets */
/*---------------------------------------------------------------------------------------------*/
assign evt_o = flgs_slave.evt[7:0];
assign clear_o = clear;
assign clear_o = clear;

endmodule : redmule_ctrl
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