Skip to content

Commit

Permalink
Merge pull request #2 from pulp-platform/ro_wo_requests
Browse files Browse the repository at this point in the history 
Add parameter to configure AXI ports as read-write or read-/write-only
  • Loading branch information
@micprog
micprog authored Aug 6, 2024
2 parents b0137e6 + c303b4d commit b9af1c4
Show file tree
Hide file tree
Showing 4 changed files with 159 additions and 78 deletions.
6 changes: 0 additions & 6 deletions .github/verible.waiver
View file

This file was deleted.

2 changes: 1 addition & 1 deletion .github/workflows/lint.yml
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,6 +24,6 @@ jobs:
./src
./test
exclude_paths:
extra_args: "--waiver_files .github/verible.waiver --rules=-interface-name-style --lint_fatal --parse_fatal"
extra_args: "--rules=-interface-name-style --lint_fatal --parse_fatal"
github_token: ${{ secrets.GITHUB_TOKEN }}
reviewdog_reporter: github-check
228 changes: 157 additions & 71 deletions src/axi_memory_island_wrap.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -26,6 +26,11 @@ module axi_memory_island_wrap #(
/// Number of Wide Ports
parameter int unsigned NumWideReq = 0,

/// Indicates corresponding narrow requestor supports read/write (0 for read-only/write-only)
parameter bit [NumNarrowReq-1:0] NarrowRW = '1,
/// Indicates corresponding narrow requestor supports read/write (0 for read-only/write-only)
parameter bit [NumWideReq-1:0] WideRW = '1,

/// Spill Narrow
parameter int unsigned SpillNarrowReqEntry = 0,
parameter int unsigned SpillNarrowRspEntry = 0,
Expand All @@ -51,6 +56,7 @@ module axi_memory_island_wrap #(
parameter int unsigned NarrowExtraBF = 1,
/// Words per memory bank. (Total number of banks is (WideWidth/NarrowWidth)*NumWideBanks)
parameter int unsigned WordsPerBank = 1024,
// verilog_lint: waive explicit-parameter-storage-type
parameter MemorySimInit = "none"
) (
input logic clk_i,
Expand All @@ -66,83 +72,163 @@ module axi_memory_island_wrap #(
localparam int unsigned NarrowStrbWidth = NarrowDataWidth/8;
localparam int unsigned WideStrbWidth = WideDataWidth/8;

logic [2*NumNarrowReq-1:0] narrow_req;
logic [2*NumNarrowReq-1:0] narrow_gnt;
logic [2*NumNarrowReq-1:0][ AddrWidth-1:0] narrow_addr;
logic [2*NumNarrowReq-1:0][NarrowDataWidth-1:0] narrow_wdata;
logic [2*NumNarrowReq-1:0][NarrowStrbWidth-1:0] narrow_strb;
logic [2*NumNarrowReq-1:0] narrow_we;
logic [2*NumNarrowReq-1:0] narrow_rvalid;
logic [2*NumNarrowReq-1:0][NarrowDataWidth-1:0] narrow_rdata;

logic [ 2*NumWideReq-1:0] wide_req;
logic [ 2*NumWideReq-1:0] wide_gnt;
logic [ 2*NumWideReq-1:0][ AddrWidth-1:0] wide_addr;
logic [ 2*NumWideReq-1:0][ WideDataWidth-1:0] wide_wdata;
logic [ 2*NumWideReq-1:0][ WideStrbWidth-1:0] wide_strb;
logic [ 2*NumWideReq-1:0] wide_we;
logic [ 2*NumWideReq-1:0] wide_rvalid;
logic [ 2*NumWideReq-1:0][ WideDataWidth-1:0] wide_rdata;
localparam int unsigned InternalNumNarrow = NumNarrowReq + $countones(NarrowRW);
localparam int unsigned InternalNumWide = NumWideReq + $countones(WideRW);

localparam int unsigned NarrowMemRspLatency = SpillNarrowReqEntry +
SpillNarrowReqRouted +
SpillReqBank +
SpillRspBank +
SpillNarrowRspRouted +
SpillNarrowRspEntry +
1;
localparam int unsigned WideMemRspLatency = SpillWideReqEntry +
SpillWideReqRouted +
SpillWideReqSplit +
SpillReqBank +
SpillRspBank +
SpillWideRspSplit +
SpillWideRspRouted +
SpillWideRspEntry +
1;

logic [InternalNumNarrow-1:0] narrow_req;
logic [InternalNumNarrow-1:0] narrow_gnt;
logic [InternalNumNarrow-1:0][ AddrWidth-1:0] narrow_addr;
logic [InternalNumNarrow-1:0][NarrowDataWidth-1:0] narrow_wdata;
logic [InternalNumNarrow-1:0][NarrowStrbWidth-1:0] narrow_strb;
logic [InternalNumNarrow-1:0] narrow_we;
logic [InternalNumNarrow-1:0] narrow_rvalid;
logic [InternalNumNarrow-1:0][NarrowDataWidth-1:0] narrow_rdata;

logic [ InternalNumWide-1:0] wide_req;
logic [ InternalNumWide-1:0] wide_gnt;
logic [ InternalNumWide-1:0][ AddrWidth-1:0] wide_addr;
logic [ InternalNumWide-1:0][ WideDataWidth-1:0] wide_wdata;
logic [ InternalNumWide-1:0][ WideStrbWidth-1:0] wide_strb;
logic [ InternalNumWide-1:0] wide_we;
logic [ InternalNumWide-1:0] wide_rvalid;
logic [ InternalNumWide-1:0][ WideDataWidth-1:0] wide_rdata;


for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_conv
axi_to_mem_split #(
.axi_req_t ( axi_narrow_req_t ),
.axi_resp_t ( axi_narrow_rsp_t ),
.AddrWidth ( AddrWidth ),
.AxiDataWidth ( NarrowDataWidth ),
.IdWidth ( AxiNarrowIdWidth ),
.MemDataWidth ( NarrowDataWidth ),
.BufDepth ( 2 ),
.HideStrb ( 1'b0 ),
.OutFifoDepth ( 1 )
) i_narrow_conv (
.clk_i,
.rst_ni,
.test_i ( '0 ),
.busy_o (),
.axi_req_i ( axi_narrow_req_i[ i ] ),
.axi_resp_o ( axi_narrow_rsp_o[ i ] ),
.mem_req_o ( narrow_req [2*i+:2] ),
.mem_gnt_i ( narrow_gnt [2*i+:2] ),
.mem_addr_o ( narrow_addr [2*i+:2] ),
.mem_wdata_o ( narrow_wdata [2*i+:2] ),
.mem_strb_o ( narrow_strb [2*i+:2] ),
.mem_atop_o (),
.mem_we_o ( narrow_we [2*i+:2] ),
.mem_rvalid_i ( narrow_rvalid [2*i+:2] ),
.mem_rdata_i ( narrow_rdata [2*i+:2] )
);
localparam int unsigned Id = i + $countones(NarrowRW[i:0]);
if (NarrowRW[i]) begin : gen_split_conv
axi_to_mem_split #(
.axi_req_t ( axi_narrow_req_t ),
.axi_resp_t ( axi_narrow_rsp_t ),
.AddrWidth ( AddrWidth ),
.AxiDataWidth ( NarrowDataWidth ),
.IdWidth ( AxiNarrowIdWidth ),
.MemDataWidth ( NarrowDataWidth ),
.BufDepth ( 1 + NarrowMemRspLatency ),
.HideStrb ( 1'b0 ),
.OutFifoDepth ( 1 )
) i_narrow_conv (
.clk_i,
.rst_ni,
.test_i ( '0 ),
.busy_o (),
.axi_req_i ( axi_narrow_req_i[i ] ),
.axi_resp_o ( axi_narrow_rsp_o[i ] ),
.mem_req_o ( narrow_req [Id-:2] ),
.mem_gnt_i ( narrow_gnt [Id-:2] ),
.mem_addr_o ( narrow_addr [Id-:2] ),
.mem_wdata_o ( narrow_wdata [Id-:2] ),
.mem_strb_o ( narrow_strb [Id-:2] ),
.mem_atop_o (),
.mem_we_o ( narrow_we [Id-:2] ),
.mem_rvalid_i ( narrow_rvalid [Id-:2] ),
.mem_rdata_i ( narrow_rdata [Id-:2] )
);
end else begin : gen_single_conv
axi_to_mem #(
.axi_req_t ( axi_narrow_req_t ),
.axi_resp_t ( axi_narrow_rsp_t ),
.AddrWidth ( AddrWidth ),
.AxiDataWidth ( NarrowDataWidth ),
.IdWidth ( AxiNarrowIdWidth ),
.NumBanks ( 1 ),
.BufDepth ( 1 + NarrowMemRspLatency ),
.HideStrb ( 1'b0 ),
.OutFifoDepth ( 1 )
) i_narrow_conv (
.clk_i,
.rst_ni,
.busy_o (),
.axi_req_i ( axi_narrow_req_i[i ] ),
.axi_resp_o ( axi_narrow_rsp_o[i ] ),
.mem_req_o ( narrow_req [Id] ),
.mem_gnt_i ( narrow_gnt [Id] ),
.mem_addr_o ( narrow_addr [Id] ),
.mem_wdata_o ( narrow_wdata [Id] ),
.mem_strb_o ( narrow_strb [Id] ),
.mem_atop_o (),
.mem_we_o ( narrow_we [Id] ),
.mem_rvalid_i ( narrow_rvalid [Id] ),
.mem_rdata_i ( narrow_rdata [Id] )
);
end
end

for (genvar i = 0; i < NumWideReq; i++) begin : gen_wide_conv
axi_to_mem_split #(
.axi_req_t ( axi_wide_req_t ),
.axi_resp_t ( axi_wide_rsp_t ),
.AddrWidth ( AddrWidth ),
.AxiDataWidth ( WideDataWidth ),
.IdWidth ( AxiWideIdWidth ),
.MemDataWidth ( WideDataWidth ),
.BufDepth ( 2 ),
.HideStrb ( 1'b0 ),
.OutFifoDepth ( 1 )
) i_wide_conv (
.clk_i,
.rst_ni,
.test_i ( '0 ),
.busy_o (),
.axi_req_i ( axi_wide_req_i[ i ] ),
.axi_resp_o ( axi_wide_rsp_o[ i ] ),
.mem_req_o ( wide_req [2*i+:2] ),
.mem_gnt_i ( wide_gnt [2*i+:2] ),
.mem_addr_o ( wide_addr [2*i+:2] ),
.mem_wdata_o ( wide_wdata [2*i+:2] ),
.mem_strb_o ( wide_strb [2*i+:2] ),
.mem_atop_o (),
.mem_we_o ( wide_we [2*i+:2] ),
.mem_rvalid_i ( wide_rvalid [2*i+:2] ),
.mem_rdata_i ( wide_rdata [2*i+:2] )
);
localparam int unsigned Id = i + $countones(WideRW[i:0]);
if (WideRW[i]) begin : gen_split_conv
axi_to_mem_split #(
.axi_req_t ( axi_wide_req_t ),
.axi_resp_t ( axi_wide_rsp_t ),
.AddrWidth ( AddrWidth ),
.AxiDataWidth ( WideDataWidth ),
.IdWidth ( AxiWideIdWidth ),
.MemDataWidth ( WideDataWidth ),
.BufDepth ( 1 + WideMemRspLatency ),
.HideStrb ( 1'b0 ),
.OutFifoDepth ( 1 )
) i_wide_conv (
.clk_i,
.rst_ni,
.test_i ( '0 ),
.busy_o (),
.axi_req_i ( axi_wide_req_i[i ] ),
.axi_resp_o ( axi_wide_rsp_o[i ] ),
.mem_req_o ( wide_req [Id-:2] ),
.mem_gnt_i ( wide_gnt [Id-:2] ),
.mem_addr_o ( wide_addr [Id-:2] ),
.mem_wdata_o ( wide_wdata [Id-:2] ),
.mem_strb_o ( wide_strb [Id-:2] ),
.mem_atop_o (),
.mem_we_o ( wide_we [Id-:2] ),
.mem_rvalid_i ( wide_rvalid [Id-:2] ),
.mem_rdata_i ( wide_rdata [Id-:2] )
);
end else begin : gen_single_conv
axi_to_mem #(
.axi_req_t ( axi_wide_req_t ),
.axi_resp_t ( axi_wide_rsp_t ),
.AddrWidth ( AddrWidth ),
.AxiDataWidth ( WideDataWidth ),
.IdWidth ( AxiWideIdWidth ),
.NumBanks ( 1 ),
.BufDepth ( 1 + WideMemRspLatency ),
.HideStrb ( 1'b0 ),
.OutFifoDepth ( 1 )
) i_wide_conv (
.clk_i,
.rst_ni,
.busy_o (),
.axi_req_i ( axi_wide_req_i[i ] ),
.axi_resp_o ( axi_wide_rsp_o[i ] ),
.mem_req_o ( wide_req [Id] ),
.mem_gnt_i ( wide_gnt [Id] ),
.mem_addr_o ( wide_addr [Id] ),
.mem_wdata_o ( wide_wdata [Id] ),
.mem_strb_o ( wide_strb [Id] ),
.mem_atop_o (),
.mem_we_o ( wide_we [Id] ),
.mem_rvalid_i ( wide_rvalid [Id] ),
.mem_rdata_i ( wide_rdata [Id] )
);
end
end


Expand Down
1 change: 1 addition & 0 deletions src/memory_island_core.sv
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@ module memory_island_core #(
parameter int unsigned SpillReqBank = 0,
parameter int unsigned SpillRspBank = 0,

// verilog_lint: waive explicit-parameter-storage-type
parameter MemorySimInit = "none",

/// Relinquish narrow priority after x cycles, 0 for never. Requires SpillNarrowReqRouted==0.
Expand Down

0 comments on commit b9af1c4

Please sign in to comment.