fixup! Bump cheshire, safety island (w/ axi-rt, bus_err_unit, atops)

hw/cfg/spatz_carfield.hjson

@@ -0,0 +1,99 @@
+// Copyright 2020 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// Cluster configuration for a simple system.
+{
+ cluster: {
+ boot_addr: 4096, // 0x1000
+ cluster_base_addr: 1358954496, // 0x51000000
+ cluster_base_offset: 0, // 0x0
+ cluster_base_hartid: 16,
+ addr_width: 48,
+ data_width: 64,
+ id_width_in: 6,
+ id_width_out: 2,
+ user_width: 9,
+ axi_cdc_enable: true,
+ sw_rst_enable: true,
+ axi_isolate_enable: true,
+ tcdm: {
+ size: 128,
+ banks: 16,
+ },
+ cluster_periph_size: 64, // kB
+ dma_data_width: 64,
+ dma_axi_req_fifo_depth: 3,
+ dma_req_fifo_depth: 3,
+ // Spatz parameters
+ vlen: 512,
+ n_fpu: 4,
+ n_ipu: 1,
+ spatz_fpu: true,
+ // Timing parameters
+ timing: {
+ lat_comp_fp32: 2,
+ lat_comp_fp64: 3,
+ lat_comp_fp16: 1,
+ lat_comp_fp16_alt: 1,
+ lat_comp_fp8: 0,
+ lat_comp_fp8_alt: 0,
+ lat_noncomp: 1,
+ lat_conv: 2,
+ lat_sdotp: 3,
+ fpu_pipe_config: "BEFORE"
+ xbar_latency: "CUT_ALL_PORTS",
+
+ register_tcdm_cuts: true,
+ register_core_req: true,
+ register_core_rsp: true,
+ register_offload_req: false,
+ register_offload_rsp: true
+ },
+ cores: [
+ { $ref: "#/dma_core_template" },
+ { $ref: "#/compute_core_template" },
+ ],
+ icache: {
+ size: 4, // total instruction cache size in kByte
+ sets: 2, // number of ways
+ cacheline: 128 // word size in bits
+ }
+ }
+
+ dram: {
+ // 0x8000_0000
+ address: 2147483648,
+ // 0x8000_0000
+ length: 2147483648
+ },
+ peripherals: {
+ },
+
+ // Templates.
+
+ compute_core_template: {
+ isa: "rv32imafd",
+ xf16: true,
+ xf8: true,
+ xfdotp: true,
+ xdma: false,
+ num_int_outstanding_loads: 1,
+ num_int_outstanding_mem: 4,
+ num_spatz_outstanding_loads: 4,
+ num_dtlb_entries: 1,
+ num_itlb_entries: 1
+ },
+ dma_core_template: {
+ isa: "rv32imafd",
+ xdma: true
+ xf16: true,
+ xf8: true,
+ xfdotp: true,
+ num_int_outstanding_loads: 1,
+ num_int_outstanding_mem: 4,
+ num_spatz_outstanding_loads: 4,
+ num_dtlb_entries: 1,
+ num_itlb_entries: 1
+ }
+}