treewide: Add bare-metal offload to safety island in carfield

* Standalone offload (JTAG/Serial Link)
* CVA6-driven offload
* Update README.md

.github/workflows/lint.yml

@@ -29,6 +29,7 @@ jobs:
  sw/include/regs/*.h
  .dir-locals.el
  utils/*
+ scripts/*
 
  lint-sv:
  runs-on: ubuntu-latest

.gitignore

@@ -9,7 +9,7 @@ work/
 *.log
 *.wlf
 /.venv/
-
+sw/tests/bare-metal/safed/*.h
 
 # Created by https://www.toptal.com/developers/gitignore/api/python
 # Edit at https://www.toptal.com/developers/gitignore?templates=python

Bender.local

@@ -6,7 +6,7 @@ overrides:
  axi: { git: https://github.com/pulp-platform/axi.git , rev: 02307cf26de40c713212148abb947fef87babd61 } # branch: michaero/detailed_mem-rebase, which is rebased on top of the branch axi_rt-tbenz
  apb: { git: "https://github.com/pulp-platform/apb.git" , version: =0.2.3 }
  register_interface: { git: "https://github.com/pulp-platform/register_interface.git" , rev: 2bb08879bc2ceabe2b6a0dc283753048a739e27b } # branch main until new version tag newer than v0.4.0
- redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git" , rev: "6e10650b50c7b40f7f81602acf61526330c4d69d" } # branch: michaero/hmr-alt
+ redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git" , rev: "6a011b6f5acf3eca202ed847d6c64474a0bc7cb5" } # branch: michaero/hmr-alt
  tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git" , version: =0.2.11 }
  riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git" , version: =0.8.0 }
  idma: { git: "https://github.com/pulp-platform/idma.git" , rev: 437ffa9 }

Bender.lock

@@ -64,15 +64,6 @@ packages:
  dependencies:
  - axi
  - common_cells
- axi_obi:
- revision: 87bb718809fb5a20f8e5bad537fdf43aeef6db2a
- version: null
- source:
- Git: [email protected]:carfield/axi_obi.git
- dependencies:
- - axi
- - common_cells
- - obi
  axi_riscv_atomics:
  revision: 97dcb14ef057cbe5bd70dda2060b5bb9e7e04c6d
  version: 0.7.0
@@ -126,7 +117,7 @@ packages:
  - register_interface
  - tech_cells_generic
  cheshire:
- revision: e5fc1ea4035cbb99a32c7d49f39745861df1c152
+ revision: 9627d111085fb93a06d9ad24ecc04e017366605c
  version: null
  source:
  Git: https://github.com/pulp-platform/cheshire.git
@@ -151,7 +142,7 @@ packages:
  revision: bed98f88761ca86706c36c4c33ac600d88c42373
  version: null
  source:
- Git: https://github.com/pulp-platform/clic.git
+ Git: https://github.com/pulp-platform/clic
  dependencies:
  - common_cells
  - register_interface
@@ -189,7 +180,7 @@ packages:
  revision: 9c07fa860593b2caabd9b5681740c25fac04b878
  version: 0.2.3
  source:
- Git: https://github.com/pulp-platform/common_verification
+ Git: https://github.com/pulp-platform/common_verification.git
  dependencies: []
  cv32e40p:
  revision: 9b77611a1d0c681f4819798d95422b0b895528a2
@@ -413,7 +404,7 @@ packages:
  - hwpe-stream
  - tech_cells_generic
  redundancy_cells:
- revision: 6e10650b50c7b40f7f81602acf61526330c4d69d
+ revision: 6a011b6f5acf3eca202ed847d6c64474a0bc7cb5
  version: null
  source:
  Git: https://github.com/pulp-platform/redundancy_cells.git
@@ -449,14 +440,14 @@ packages:
  - common_cells
  - tech_cells_generic
  safety_island:
- revision: 60e768a3ef29f47339e31674d497293f5a768893
+ revision: b681e050d266aae04cdc54f9db879e3e64dff206
  version: null
  source:
  Git: [email protected]:carfield/safety-island.git
  dependencies:
  - apb
  - axi
- - axi_obi
+ - axi_riscv_atomics
  - bus_err_unit
  - clic
  - cluster_interconnect

Bender.yml

@@ -12,10 +12,10 @@ package:
 dependencies:
  register_interface: { git: https://github.com/pulp-platform/register_interface.git, rev: 2bb08879bc2ceabe2b6a0dc283753048a739e27b } # branch: main until newer version tag later than v0.4.0
  axi: { git: https://github.com/pulp-platform/axi.git, version: 0.39.0-beta.9 } # overridden in Bender.local to use axi-rt feature
- cheshire: { git: https://github.com/pulp-platform/cheshire.git, rev: e5fc1ea4035cbb99a32c7d49f39745861df1c152 } # branch: aottaviano/cva6-clic
+ cheshire: { git: https://github.com/pulp-platform/cheshire.git, rev: 9627d111085fb93a06d9ad24ecc04e017366605c } # branch: aottaviano/vip-rebase, on top of aottaviano/cva6-clic
  hyperbus: { git: https://github.com/pulp-platform/hyperbus.git, rev: 2adb7271438cdb96c19fbaf3e2a6bf89ffeee568 } # branch: lv/phys_in_use
  car_l2: { git: [email protected]:carfield/carfield_l2_mem.git, rev: 4239b2a510d65aa110bcc8a070e434cabd1a8b9a } # branch: main
- safety_island: { git: [email protected]:carfield/safety-island.git, rev: 60e768a3ef29f47339e31674d497293f5a768893 } # branch: atops
+ safety_island: { git: [email protected]:carfield/safety-island.git, rev: b681e050d266aae04cdc54f9db879e3e64dff206 } # branch: main
  pulp_cluster: { git: https://github.com/pulp-platform/pulp_cluster.git, rev: 314f9a04f8dad4a5eeb0b9e8ad84898c6dc3f81e } # branch: yt/carfield-integration
  opentitan: { git: https://github.com/alsaqr-platform/opentitan.git, rev: 5ce64a6225e971c1e00ece29aa485f23a31aa7b2 } # branch: carfield
  mailbox_unit: { git: [email protected]:pulp-platform/mailbox_unit.git, version: 1.1.0 }
@@ -32,6 +32,9 @@ workspace:
  package_links:
  cheshire: cheshire
  spatz: spatz
+ safety_island: safety_island
+ opentitan: opentitan
+ pulp_cluster: pulp_cluster
 
 sources:
  # Source files grouped in levels. Files in level 0 have no dependencies on files in this
@@ -52,6 +55,7 @@ sources:
  - target: test
  files:
  - tb/hyp_vip/s27ks0641.v
+ - tb/vip_carfield_soc.sv
  - tb/carfield_fix.sv
  - tb/carfield_tb.sv
 
@@ -62,7 +66,7 @@ sources:
  - target: all(synthesis, not(fpga))
  files:
  - target/synth/carfield_synth_wrap.sv
- 
+
  - target: all(xilinx, fpga)
  files:
  - target/xilinx/src/carfield_top_xilinx.sv

README.md

@@ -18,8 +18,10 @@ To handle project dependencies, you can use
 
 ## Carfield Initialization
 To initialize Carfield, do the following:
- * Export the `RISCV` environment variable to the RISC-V toolchain. To work on IIS machines,
- do `export RISCV=/usr/pack/riscv-1.0-kgf/riscv64-gcc-11.2.0`.
+ * Check that you have a RISCV toolchain for both RV64 and RV32 ISAs. For ETH, type:
+ ```
+ source scripts/env-iis.sh
+ ```
  * Execute the command:
 
  ```
@@ -40,6 +42,8 @@ To initialize Carfield, do the following:
 
 Follow these steps to launch a Carfield simulation:
 
+### Compile HW and SW
+
 * Generate the compile scripts for Questasim and compile Carfield.
 
  ```
@@ -55,9 +59,11 @@ Follow these steps to launch a Carfield simulation:
  make car-sw-build
  ```
 
-* Simulate a binary in RTL. The current supported bootmodes from Cheshire are:
+### System bootmodes
+
+* The current supported bootmodes from Cheshire are:
 
- | Bootmode | Preload mode | Action |
+ | `CHS_BOOTMODE` | `CHS_PRELMODE` | Action |
  | --- | --- | --- |
  | 0 | 0 | Passive bootmode, JTAG preload |
  | 0 | 1 | Passive bootmode, Serial Link preload |
@@ -66,18 +72,33 @@ Follow these steps to launch a Carfield simulation:
  | 2 | - | Autonomous bootmode, SPI flash |
  | 3 | - | Autonomous bootmode, I2C EEPROM |
 
- `Bootmode` indicates the available bootmodes in Cheshire, while `Preload mode`
- indicates the type of preload, if any is needed. For RTL simulation, bootmodes
- 0, 2 and 3 are supported. SPI SD card bootmode is supported on FPGA emulation.
+ `Bootmode` indicates the available bootmodes in Cheshire, while `Preload mode` indicates the type
+ of preload, if any is needed. For RTL simulation, bootmodes 0, 2 and 3 are supported. SPI SD card
+ bootmode is supported on FPGA emulation.
 
- To launch an RTL simulation with the selected boot and preload modes, type:
+* The current supported bootmodes ffrom the Safety Island are:
 
- | Bootmode | Command |
+ | `SAFED_BOOTMODE` | Action |
  | --- | --- |
- | 0 | `make car-hw-sim BOOTMODE=<bootmode> PRELMODE=<prelmode> CHS_BINARY=<chs_binary_path>.car.elf SECD_BINARY=<secd_binary_path> SAFED_BINARY=<safed_binary_path>` |
- | 1, 2, 3 | `make car-hw-sim BOOTMODE=<bootmode> PRELMODE=<prelmode> CHS_IMAGE=<chs_binary_path>.car.memh` |
+ | 0 | Passive bootmode, JTAG preload |
+ | 1 | Passive bootmode, Serial Link preload |
+
+### Simulation
+
+To launch an RTL simulation with the selected boot/preload modes for the island of choice, type:
+
+
+* For cheshire in passive bootmode (`CHS_BOOTMODE=0`), set `CHS_BINARY` for Cheshire
+
+```
+make car-hw-sim CHS_BOOTMODE=<chs_bootmode> CHS_PRELMODE=<chs_prelmode> CHS_BINARY=<chs_binary_path>.car.elf PULPCL_BINARY=<pulpcl_binary> SPATZCL_BINARY=<spatzcl_binary> SECD_BINARY=<secd_binary_path> SAFED_BOOTMODE=<safed_bootmode> SAFED_BINARY=<safed_binary_path>
+```
+
+* For cheshire in autonomous bootmode (`CHS_BOOTMODE` = {1,2,3}), set `CHS_IMAGE` for Cheshire
 
- Default is passive bootmode with serial link preload.
+```
+make car-hw-sim CHS_BOOTMODE=<chs_bootmode> CHS_PRELMODE=<chs_prelmode> CHS_IMAGE=<chs_binary_path>.car.memh PULPCL_BINARY=<pulpcl_binary> SPATZCL_BINARY=<spatzcl_binary> SECD_BINARY=<secd_binary_path> SAFED_BOOTMODE=<safed_bootmode> SAFED_BINARY=<safed_binary_path>
+```
 
 ## License
 

bender-common.mk

@@ -1,4 +1,4 @@
-# Copyright 2021 ETH Zurich and University of Bologna.
+# Copyright 2023 ETH Zurich and University of Bologna.
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 #

bender-safed.mk

@@ -0,0 +1,8 @@
+# Copyright 2023 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Author: Alessandro Ottaviano <[email protected]>
+
+# bender defines
+safed_defs += -D TARGET_SIMULATION

bender-synth.mk

@@ -1,4 +1,4 @@
-# Copyright 2021 ETH Zurich and University of Bologna.
+# Copyright 2023 ETH Zurich and University of Bologna.
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 #