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hw: Fix AXI cdc and isolate bounds
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@alex96295
alex96295 committed Jul 11, 2023
1 parent 03b51d0 commit 46bf1db
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36 changes: 18 additions & 18 deletions hw/carfield.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -433,24 +433,24 @@ logic [ LlcWWidth-1:0] llc_w_data;
logic [ LogDepth:0] llc_w_wptr;
logic [ LogDepth:0] llc_w_rptr;

// All AXI Slaves (except the Integer Cluster)
logic [iomsb(Cfg.AxiExtNumSlv-1):0][CarfieldAxiSlvAwWidth-1:0] axi_slv_ext_aw_data;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_aw_wptr;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_aw_rptr;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ CarfieldAxiSlvWWidth-1:0] axi_slv_ext_w_data ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_w_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_w_rptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ CarfieldAxiSlvBWidth-1:0] axi_slv_ext_b_data ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_b_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_b_rptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][CarfieldAxiSlvArWidth-1:0] axi_slv_ext_ar_data;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_ar_wptr;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_ar_rptr;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ CarfieldAxiSlvRWidth-1:0] axi_slv_ext_r_data ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_r_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_slv_ext_r_rptr ;

// All AXI Slaves (except the Integer Cluster)
// All AXI Slaves (except the Integer Cluster and the Mailbox)
logic [iomsb(Cfg.AxiExtNumSlv-2):0][CarfieldAxiSlvAwWidth-1:0] axi_slv_ext_aw_data;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_aw_wptr;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_aw_rptr;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ CarfieldAxiSlvWWidth-1:0] axi_slv_ext_w_data ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_w_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_w_rptr ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ CarfieldAxiSlvBWidth-1:0] axi_slv_ext_b_data ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_b_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_b_rptr ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][CarfieldAxiSlvArWidth-1:0] axi_slv_ext_ar_data;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_ar_wptr;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_ar_rptr;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ CarfieldAxiSlvRWidth-1:0] axi_slv_ext_r_data ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_r_wptr ;
logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_slv_ext_r_rptr ;

// All AXI Masters (except the Integer Cluster)
logic [iomsb(Cfg.AxiExtNumMst-1):0][CarfieldAxiMstAwWidth-1:0] axi_mst_ext_aw_data;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_aw_wptr;
logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_mst_ext_aw_rptr;
Expand Down
16 changes: 8 additions & 8 deletions hw/carfield_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -40,8 +40,8 @@ typedef enum byte_bt {
EthernetSlvIdx = 'd3,
PeriphsSlvIdx = 'd4,
FPClusterSlvIdx = 'd5,
MailboxSlvIdx = 'd6,
IntClusterSlvIdx = 'd7
IntClusterSlvIdx = 'd6,
MailboxSlvIdx = 'd7
} axi_slv_idx_t;

typedef enum byte_bt {
Expand Down Expand Up @@ -231,27 +231,27 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{
AxiExtNumSlv : AxiNumExtSlv,
AxiExtNumRules : AxiNumExtSlv,
// External AXI region map
AxiExtRegionIdx : '{0, 0, 0, 0, 0, 0, 0, 0, IntClusterSlvIdx ,
AxiExtRegionIdx : '{0, 0, 0, 0, 0, 0, 0, 0, MailboxSlvIdx ,
IntClusterSlvIdx ,
FPClusterSlvIdx ,
PeriphsSlvIdx ,
EthernetSlvIdx ,
MailboxSlvIdx ,
SafetyIslandSlvIdx,
L2Port2SlvIdx ,
L2Port1SlvIdx },
AxiExtRegionStart : '{0, 0, 0, 0, 0, 0, 0, 0, IntClusterBase ,
AxiExtRegionStart : '{0, 0, 0, 0, 0, 0, 0, 0, MailboxBase ,
IntClusterBase ,
FPClusterBase ,
PeriphsBase ,
EthernetBase ,
MailboxBase ,
SafetyIslandBase,
L2Port2Base ,
L2Port1Base },
AxiExtRegionEnd : '{0, 0, 0, 0, 0, 0, 0, 0, IntClusterEnd ,
AxiExtRegionEnd : '{0, 0, 0, 0, 0, 0, 0, 0, MailboxEnd ,
IntClusterEnd ,
FPClusterEnd ,
PeriphsEnd ,
EthernetEnd ,
MailboxEnd ,
SafetyIslandEnd,
L2Port2End ,
L2Port1End },
Expand Down
49 changes: 26 additions & 23 deletions hw/cheshire_wrap.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -182,25 +182,26 @@ module cheshire_wrap
output logic [ LlcWWidth-1:0] llc_mst_w_data_o ,
output logic [ LogDepth:0] llc_mst_w_wptr_o ,
input logic [ LogDepth:0] llc_mst_w_rptr_i ,
// External AXI slave devices (except the Integer Cluster)
input logic [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_isolate_i,
output logic [iomsb(Cfg.AxiExtNumSlv):0] axi_ext_slv_isolated_o,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ExtSlvArWidth-1:0] axi_ext_slv_ar_data_o,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_ar_wptr_o,
input logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_ar_rptr_i,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ExtSlvAwWidth-1:0] axi_ext_slv_aw_data_o,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_aw_wptr_o,
input logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_aw_rptr_i,
input logic [iomsb(Cfg.AxiExtNumSlv-1):0][ ExtSlvBWidth-1:0] axi_ext_slv_b_data_i ,
input logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_b_wptr_i ,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_b_rptr_o ,
input logic [iomsb(Cfg.AxiExtNumSlv-1):0][ ExtSlvRWidth-1:0] axi_ext_slv_r_data_i ,
input logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_r_wptr_i ,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_r_rptr_o ,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ ExtSlvWWidth-1:0] axi_ext_slv_w_data_o ,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_w_wptr_o ,
input logic [iomsb(Cfg.AxiExtNumSlv-1):0][ LogDepth:0] axi_ext_slv_w_rptr_i ,
// External AXI master devices (except the Integer Cluster)
// External AXI isolate slave Ports (except the Mailbox)
input logic [iomsb(Cfg.AxiExtNumSlv-1):0] axi_ext_slv_isolate_i,
output logic [iomsb(Cfg.AxiExtNumSlv-1):0] axi_ext_slv_isolated_o,
// External async AXI slave Ports (except the Integer Cluster and the Mailbox)
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ExtSlvArWidth-1:0] axi_ext_slv_ar_data_o,
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_ar_wptr_o,
input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_ar_rptr_i,
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ExtSlvAwWidth-1:0] axi_ext_slv_aw_data_o,
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_aw_wptr_o,
input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_aw_rptr_i,
input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ ExtSlvBWidth-1:0] axi_ext_slv_b_data_i ,
input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_b_wptr_i ,
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_b_rptr_o ,
input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ ExtSlvRWidth-1:0] axi_ext_slv_r_data_i ,
input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_r_wptr_i ,
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_r_rptr_o ,
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ ExtSlvWWidth-1:0] axi_ext_slv_w_data_o ,
output logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_w_wptr_o ,
input logic [iomsb(Cfg.AxiExtNumSlv-2):0][ LogDepth:0] axi_ext_slv_w_rptr_i ,
// External async AXI master Ports (except the Integer Cluster)
input logic [iomsb(Cfg.AxiExtNumMst-1):0][ExtMstArWidth-1:0] axi_ext_mst_ar_data_i,
input logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_ar_wptr_i,
output logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_ar_rptr_o,
Expand All @@ -216,7 +217,7 @@ module cheshire_wrap
input logic [iomsb(Cfg.AxiExtNumMst-1):0][ ExtMstWWidth-1:0] axi_ext_mst_w_data_i ,
input logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_w_wptr_i ,
output logic [iomsb(Cfg.AxiExtNumMst-1):0][ LogDepth:0] axi_ext_mst_w_rptr_o ,
// Integer Cluster Slave Port
// Integer Cluster async Slave Port
output logic [IntClusterAxiSlvAwWidth-1:0] axi_slv_intcluster_aw_data_o,
output logic [ LogDepth:0] axi_slv_intcluster_aw_wptr_o,
input logic [ LogDepth:0] axi_slv_intcluster_aw_rptr_i,
Expand All @@ -232,7 +233,7 @@ module cheshire_wrap
input logic [ IntClusterAxiSlvRWidth-1:0] axi_slv_intcluster_r_data_i ,
input logic [ LogDepth:0] axi_slv_intcluster_r_wptr_i ,
output logic [ LogDepth:0] axi_slv_intcluster_r_rptr_o ,
// Integer Cluster Master Port
// Integer Cluster async Master Port
input logic [IntClusterAxiMstAwWidth-1:0] axi_mst_intcluster_aw_data_i,
input logic [ LogDepth:0] axi_mst_intcluster_aw_wptr_i,
output logic [ LogDepth:0] axi_mst_intcluster_aw_rptr_o,
Expand Down Expand Up @@ -441,7 +442,8 @@ cheshire_soc #(
.vga_blue_o
);

// Cheshire's AXI master cdc and isolate generation, but integer cluster and mailboxes
// Cheshire's AXI master cdc generation, except for the Integer Cluster (slave 6) and the Mailbox
// (slave 7)
for (genvar i = 0; i < Cfg.AxiExtNumSlv - 2; i++) begin: gen_ext_slv_src_cdc
axi_isolate #(
.NumPending ( Cfg.AxiMaxSlvTrans ),
Expand Down Expand Up @@ -498,7 +500,8 @@ for (genvar i = 0; i < Cfg.AxiExtNumSlv - 2; i++) begin: gen_ext_slv_src_cdc
);
end

// Cheshire's AXI slave cdc and isolate generation, but integer cluster

// Cheshire's AXI slave cdc and isolate generation, except for the Integer Cluster (slave 7)
for (genvar i = 0; i < Cfg.AxiExtNumMst - 1; i++) begin: gen_ext_mst_dst_cdc
axi_cdc_dst #(
.LogDepth ( LogDepth ),
Expand Down

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