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    292 repositories

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •36•243•23•4•Updated Oct 20, 2024Oct 20, 2024

    • morty

      Public
      A SystemVerilog source file pickler.
      rustpicklersrickandmortysystemverilog-hdl
      Rust
      •
      Apache License 2.0
      •5•51•8•2•Updated Oct 20, 2024Oct 20, 2024

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •44•191•8•22•Updated Oct 19, 2024Oct 19, 2024

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •129•365•62•9•Updated Oct 19, 2024Oct 19, 2024

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •2•14•1•0•Updated Oct 19, 2024Oct 19, 2024

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •45•272•3•7•Updated Oct 18, 2024Oct 18, 2024

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •682•15•1•9•Updated Oct 18, 2024Oct 18, 2024

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •21•56•4•4•Updated Oct 18, 2024Oct 18, 2024

    • chimera

      Public
      Python
      •
      Other
      •1•9•9•4•Updated Oct 18, 2024Oct 18, 2024

    • memory_island

      Public
      An interleaved high-throughput low-contention L2 scratchpad memory.
      SystemVerilog
      •
      Other
      •0•1•4•3•Updated Oct 18, 2024Oct 18, 2024

    • tech_cells_generic

      Public
      Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
      SystemVerilog
      •
      Other
      •30•28•1•5•Updated Oct 18, 2024Oct 18, 2024

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      Other
      •300•7•0•4•Updated Oct 17, 2024Oct 17, 2024

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •145•503•29•6•Updated Oct 17, 2024Oct 17, 2024

    • serial_link

      Public
      A simple, scalable, source-synchronous, all-digital DDR link
      SystemVerilog
      •
      Other
      •9•15•0•1•Updated Oct 16, 2024Oct 16, 2024

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •21•130•10•3•Updated Oct 16, 2024Oct 16, 2024

    • pulp-trainlib

      Public
      Floating-Point Optimized On-Device Learning Library for the PULP Platform.
      C
      •
      Apache License 2.0
      •15•26•4•3•Updated Oct 16, 2024Oct 16, 2024

    • ITA

      Public
      SystemVerilog
      •
      Other
      •2•9•0•1•Updated Oct 16, 2024Oct 16, 2024

    • banshee

      Public
      Rust
      •
      Apache License 2.0
      •5•16•6•0•Updated Oct 16, 2024Oct 16, 2024

    • u-boot

      Public
      Unofficial development fork of U-Boot
      C
      •10•0•0•1•Updated Oct 15, 2024Oct 15, 2024

    • opensbi

      Public
      RISC-V Open Source Supervisor Binary Interface
      C
      •
      Other
      •506•0•0•2•Updated Oct 15, 2024Oct 15, 2024

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •65•1•0•2•Updated Oct 15, 2024Oct 15, 2024

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •50•50•13•6•Updated Oct 11, 2024Oct 11, 2024

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •1•9•0•3•Updated Oct 9, 2024Oct 9, 2024

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •260•1.1k•42•13•Updated Oct 8, 2024Oct 8, 2024

    • axi_rt

      Public
      SystemVerilog
      •
      Other
      •3•2•4•0•Updated Oct 8, 2024Oct 8, 2024

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •13•5•0•6•Updated Oct 8, 2024Oct 8, 2024

    • quadrilatero

      Public
      matrix-coprocessor for RISC-V
      C
      •
      Other
      •1•10•0•0•Updated Oct 4, 2024Oct 4, 2024

    • pulp-ethernet

      Public
      SystemVerilog
      •
      Other
      •1•8•0•2•Updated Oct 4, 2024Oct 4, 2024

    • occamy

      Public
      A high-efficiency system-on-chip for floating-point compute workloads.
      Python
      •
      Apache License 2.0
      •11•16•7•1•Updated Oct 3, 2024Oct 3, 2024

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •16•69•1•2•Updated Oct 3, 2024Oct 3, 2024