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Update soc branch with changes from main #921
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Many small fixes
…stFloat produces incorrect results with Verilator
… greater than 0 rather than just 1.
Simulation fixes
Fixes the wavefile, testbench, wsim, and wally.do to correctly support function tracking the wavefile.
…ON_FPU=0, FLEN=32, XLEN=64
…ation of fround passes basic regression but fails some nightly regression cases
fixed fma testfloat issue openhwgroup#578
Regression fully running
Now need to merge do files.
Covergen doesn't produce stores and riscv-dv only generates tests
…old if. PC=0 detection is disabled for now.
Update riscv-arch-test
lint cleanup and divider optimization
Clean up unused signals for derived configurations
Files for Quad Precision Testing Support for Wally
Testbench cleanup
FPU without privilege modes + derived config fixes
…set-val so can be put back
Temporarily removing Q tests as not everyone has tests
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This PR brings the soc branch up to date with main. This will make #681 a lot less cluttered.