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wbgenplus - A WishBone3 bus device generator for Vhdl in python
Python 4 1
A small git project
C 1
modified version of the wprc sw as FAIR Timing Master
C 1 1
cocotb for vhdl/wishbone
VHDL 1
Cocotb code for VHDL topfiles and wishbone bus access
Python 1
Forked from cocotb/cocotb
Coroutine Co-simulation Test Bench