Merge pull request #8 from matan1008/bugfix/load-store-immediate-t1

Bugfix/load store immediate t1

.github/workflows/python-app.yml

@@ -16,7 +16,7 @@ jobs:
 
     strategy:
       matrix:
-        python-version: [ 3.6, 3.7, 3.8, 3.9, "3.10" ]
+        python-version: [ 3.7, 3.8, 3.9, "3.10", 3.11 ]
 
     steps:
       - uses: actions/checkout@v2

armulator/armv6/arm_v6.py

@@ -37,24 +37,29 @@ def __init__(self, config_file=path.join(path.abspath(path.dirname(__file__)), '
     def start(self):
         self.take_reset()
 
+    def format_registers(self):
+        return (
+            f"R0: 0x{self.registers.get(0):08X}\n"
+            f"R1: 0x{self.registers.get(1):08X}\n"
+            f"R2: 0x{self.registers.get(2):08X}\n"
+            f"R3: 0x{self.registers.get(3):08X}\n"
+            f"R4: 0x{self.registers.get(4):08X}\n"
+            f"R5: 0x{self.registers.get(5):08X}\n"
+            f"R6: 0x{self.registers.get(6):08X}\n"
+            f"R7: 0x{self.registers.get(7):08X}\n"
+            f"R8: 0x{self.registers.get(8):08X}\n"
+            f"R9: 0x{self.registers.get(9):08X}\n"
+            f"R10: 0x{self.registers.get(10):08X}\n"
+            f"R11: 0x{self.registers.get(11):08X}\n"
+            f"R12: 0x{self.registers.get(12):08X}\n"
+            f"SP: 0x{self.registers.get_sp():08X}\n"
+            f"LR: 0x{self.registers.get_lr():08X}\n"
+            f"PC: 0x{self.registers.pc_store_value():08X}\n"
+            f"CPSR: 0x{self.registers.cpsr.value:08X}\n"
+        )
+
     def print_registers(self):
-        print("{0}:{1}".format("R0", self.registers.get(0)))
-        print("{0}:{1}".format("R1", self.registers.get(1)))
-        print("{0}:{1}".format("R2", self.registers.get(2)))
-        print("{0}:{1}".format("R3", self.registers.get(3)))
-        print("{0}:{1}".format("R4", self.registers.get(4)))
-        print("{0}:{1}".format("R5", self.registers.get(5)))
-        print("{0}:{1}".format("R6", self.registers.get(6)))
-        print("{0}:{1}".format("R7", self.registers.get(7)))
-        print("{0}:{1}".format("R8", self.registers.get(8)))
-        print("{0}:{1}".format("R9", self.registers.get(9)))
-        print("{0}:{1}".format("R10", self.registers.get(10)))
-        print("{0}:{1}".format("R11", self.registers.get(11)))
-        print("{0}:{1}".format("R12", self.registers.get(12)))
-        print("{0}:{1}".format("SP", self.registers.get_sp()))
-        print("{0}:{1}".format("LR", self.registers.get_lr()))
-        print("{0}:{1}".format("PC", self.registers.pc_store_value()))
-        print("{0}:{1}".format("CPSR", self.registers.cpsr.value))
+        print(self.format_registers())
 
     def take_reset(self):
         self.registers.cpsr.m = 0b10011

armulator/armv6/opcodes/concrete/ldrb_immediate_thumb_t1.py

@@ -11,5 +11,4 @@ def from_bitarray(instr, processor):
         index = True
         add = True
         wback = False
-        imm32 = imm5 << 2
-        return LdrbImmediateThumbT1(instr, add=add, wback=wback, index=index, t=rt, n=rn, imm32=imm32)
+        return LdrbImmediateThumbT1(instr, add=add, wback=wback, index=index, t=rt, n=rn, imm32=imm5)

armulator/armv6/opcodes/concrete/ldrh_immediate_thumb_t1.py

@@ -11,5 +11,5 @@ def from_bitarray(instr, processor):
         index = True
         add = True
         wback = False
-        imm32 = imm5 << 2
+        imm32 = imm5 << 1
         return LdrhImmediateThumbT1(instr, add=add, wback=wback, index=index, t=rt, n=rn, imm32=imm32)

armulator/armv6/opcodes/concrete/strb_immediate_thumb_t1.py

@@ -11,5 +11,5 @@ def from_bitarray(instr, processor):
         index = True
         add = True
         wback = False
-        imm32 = imm5 * 4
+        imm32 = imm5
         return StrbImmediateThumbT1(instr, add=add, wback=wback, index=index, t=rt, n=rn, imm32=imm32)

armulator/armv6/opcodes/concrete/strh_immediate_thumb_t1.py

@@ -11,5 +11,5 @@ def from_bitarray(instr, processor):
         index = True
         add = True
         wback = False
-        imm32 = imm5 << 2
+        imm32 = imm5 << 1
         return StrhImmediateThumbT1(instr, add=add, wback=wback, index=index, t=rt, n=rn, imm32=imm32)

setup.py

@@ -27,6 +27,7 @@ def get_description():
             'Programming Language :: Python :: 3.8',
             'Programming Language :: Python :: 3.9',
             'Programming Language :: Python :: 3.10',
+            'Programming Language :: Python :: 3.11',
         ],
         keywords='arm emulator',
         packages=PACKAGES,

tests/armv6_tests/opcode_tests/test_ldrb.py

@@ -48,7 +48,7 @@ def test_ldrb_register_t1(thumb_v6_without_fetch):
 
 def test_ldrb_immediate_thumb_t1(thumb_v6_without_fetch):
     arm = thumb_v6_without_fetch
-    arm.opcode = 0b0111100001001010
+    arm.opcode = 0b0111100100001010
     arm.opcode_len = 16
     # setting Data Region registers
     arm.registers.drsrs[0].en = 1  # enabling memory region

tests/armv6_tests/opcode_tests/test_ldrh.py

@@ -48,7 +48,7 @@ def test_ldrh_register_t1(thumb_v6_without_fetch):
 
 def test_ldrh_immediate_thumb_t1(thumb_v6_without_fetch):
     arm = thumb_v6_without_fetch
-    arm.opcode = 0b1000100001001010
+    arm.opcode = 0b1000100010001010
     arm.opcode_len = 16
     # setting Data Region registers
     arm.registers.drsrs[0].en = 1  # enabling memory region

tests/armv6_tests/opcode_tests/test_strb.py

@@ -46,7 +46,7 @@ def test_strb_register_t1(thumb_v6_without_fetch):
 
 def test_strb_immediate_thumb_t1(thumb_v6_without_fetch):
     arm = thumb_v6_without_fetch
-    arm.opcode = 0b0111000001001010
+    arm.opcode = 0b0111000100001010
     arm.opcode_len = 16
     # setting Data Region registers
     arm.registers.drsrs[0].en = 1  # enabling memory region

tests/armv6_tests/opcode_tests/test_strh.py

@@ -46,7 +46,7 @@ def test_strh_register_t1(thumb_v6_without_fetch):
 
 def test_strh_immediate_thumb_t1(thumb_v6_without_fetch):
     arm = thumb_v6_without_fetch
-    arm.opcode = 0b1000000001001010
+    arm.opcode = 0b1000000010001010
     arm.opcode_len = 16
     # setting Data Region registers
     arm.registers.drsrs[0].en = 1  # enabling memory region