TODO: Support for RISC-V Star64 JH7110 SBC (Branch star64e)

.gitignore

@@ -60,3 +60,5 @@ uImage
 .vscode
 .DS_Store
 tools/gdb/__pycache__
+initrd
+init.S

arch/risc-v/include/qemu-rv/irq.h

@@ -31,8 +31,6 @@
 
 /* Map RISC-V exception code to NuttX IRQ */
 
-#define QEMU_RV_IRQ_UART0  (RISCV_IRQ_MEXT + 10)
-
-#define NR_IRQS (QEMU_RV_IRQ_UART0 + 1)
+#define NR_IRQS (RISCV_IRQ_SEXT + 127)
 
 #endif /* __ARCH_RISCV_INCLUDE_QEMU_RV_IRQ_H */

arch/risc-v/src/qemu-rv/Make.defs

@@ -27,16 +27,4 @@ HEAD_ASRC = qemu_rv_head.S
 # Specify our C code within this directory to be included
 CHIP_CSRCS  = qemu_rv_start.c qemu_rv_irq_dispatch.c qemu_rv_irq.c
 CHIP_CSRCS += qemu_rv_timerisr.c qemu_rv_allocateheap.c
-
-ifeq ($(CONFIG_BUILD_KERNEL),y)
-CHIP_CSRCS += qemu_rv_mm_init.c
-CMN_ASRCS  += qemu_rv_exception_m.S
-endif
-
-ifeq ($(CONFIG_MM_PGALLOC),y)
-CHIP_CSRCS += qemu_rv_pgalloc.c
-endif
-
-ifeq ($(CONFIG_DRIVERS_VIRTIO_NET),y)
-CHIP_CSRCS += qemu_rv_virtio.c
-endif
+CHIP_CSRCS += qemu_rv_mm_init.c qemu_rv_pgalloc.c

arch/risc-v/src/qemu-rv/chip.h

@@ -31,7 +31,6 @@
 
 #include "qemu_rv_memorymap.h"
 
-#include "hardware/qemu_rv_clint.h"
 #include "hardware/qemu_rv_memorymap.h"
 #include "hardware/qemu_rv_plic.h"
 

arch/risc-v/src/qemu-rv/hardware/qemu_rv_memorymap.h

@@ -27,8 +27,6 @@
 
 /* Register Base Address ****************************************************/
 
-#define QEMU_RV_CLINT_BASE   0x02000000
-#define QEMU_RV_ACLINT_BASE  0x02f00000
 #define QEMU_RV_PLIC_BASE    0x0c000000
 
 #endif /* __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_MEMORYMAP_H */

arch/risc-v/src/qemu-rv/hardware/qemu_rv_plic.h

@@ -31,19 +31,21 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+/* Interrupt Priority */
+
 #define QEMU_RV_PLIC_PRIORITY    (QEMU_RV_PLIC_BASE + 0x000000)
-#define QEMU_RV_PLIC_PENDING1    (QEMU_RV_PLIC_BASE + 0x001000)
-
-#ifdef CONFIG_ARCH_USE_S_MODE
-#  define QEMU_RV_PLIC_ENABLE1   (QEMU_RV_PLIC_BASE + 0x002080)
-#  define QEMU_RV_PLIC_ENABLE2   (QEMU_RV_PLIC_BASE + 0x002084)
-#  define QEMU_RV_PLIC_THRESHOLD (QEMU_RV_PLIC_BASE + 0x201000)
-#  define QEMU_RV_PLIC_CLAIM     (QEMU_RV_PLIC_BASE + 0x201004)
-#else
-#  define QEMU_RV_PLIC_ENABLE1   (QEMU_RV_PLIC_BASE + 0x002000)
-#  define QEMU_RV_PLIC_ENABLE2   (QEMU_RV_PLIC_BASE + 0x002004)
-#  define QEMU_RV_PLIC_THRESHOLD (QEMU_RV_PLIC_BASE + 0x200000)
-#  define QEMU_RV_PLIC_CLAIM     (QEMU_RV_PLIC_BASE + 0x200004)
-#endif
+
+/* Hart 1 S-Mode Interrupt Enable */
+
+#define QEMU_RV_PLIC_ENABLE1   (QEMU_RV_PLIC_BASE + 0x002100)
+#define QEMU_RV_PLIC_ENABLE2   (QEMU_RV_PLIC_BASE + 0x002104)
+
+/* Hart 1 S-Mode Priority Threshold */
+
+#define QEMU_RV_PLIC_THRESHOLD (QEMU_RV_PLIC_BASE + 0x202000)
+
+/* Hart 1 S-Mode Claim / Complete */
+
+#define QEMU_RV_PLIC_CLAIM     (QEMU_RV_PLIC_BASE + 0x202004)
 
 #endif /* __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_PLIC_H */

arch/risc-v/src/qemu-rv/qemu_rv_allocateheap.c

@@ -86,11 +86,7 @@
  *
  ****************************************************************************/
 
-#ifdef CONFIG_BUILD_KERNEL
 void up_allocate_kheap(void **heap_start, size_t *heap_size)
-#else
-void up_allocate_heap(void **heap_start, size_t *heap_size)
-#endif /* CONFIG_BUILD_KERNEL */
 {
 #if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
   /* Get the size and position of the user-space heap.

arch/risc-v/src/qemu-rv/qemu_rv_head.S

@@ -40,10 +40,40 @@
   .global __start
 
 __start:
+  /* Begin Test */
 
-  /* Load mhartid (cpuid) */
+  /* DO NOT MODIFY. Image Header expected by Linux bootloaders.
+   *
+   * This `li` instruction has no meaningful effect except that
+   * its opcode forms the magic "MZ" signature of a PE/COFF file
+   * that is required for UEFI applications.
+   *
+   * Some bootloaders check the magic "MZ" to see if the image is a valid
+   * Linux image. But modifying the bootLoader is unnecessary unless we
+   * need to do a customized secure boot. So we just put "MZ" in the
+   * header to make the bootloader happy.
+   */
+
+  c.li    s4, -13              /* Magic Signature "MZ" (2 bytes) */
+  j       real_start           /* Jump to Kernel Start (2 bytes) */
+  .long   0                    /* Executable Code padded to 8 bytes */
+  .quad   0x200000             /* Image load offset from start of RAM */
+  .quad   _ebss - __start      /* Effective size of kernel image */
+  .quad   0                    /* Kernel flags, little-endian */
+  .long   2                    /* Version of this header */
+  .long   0                    /* Reserved */
+  .quad   0                    /* Reserved */
+  .ascii  "RISCV\x00\x00\x00"  /* Magic number, "RISCV" (8 bytes) */
+  .ascii  "RSC\x05"            /* Magic number 2, "RSC\x05" (4 bytes) */
+  .long   0                    /* Reserved for PE COFF offset */
+
+real_start:
+
+  /* We assume that OpenSBI has passed Hart ID (value 1) in Register a0.
+   * But NuttX expects Hart ID to start at 0, so we subtract 1.
+   */
 
-  csrr a0, mhartid
+  addi a0, a0, -1
 
   /* Set stack pointer to the idle thread stack */
 
@@ -60,14 +90,14 @@ __start:
   li   t1, 1
 #endif
 
-  /* If a0 (mhartid) >= t1 (the number of CPUs), stop here */
+  /* If a0 (hartid) >= t1 (the number of CPUs), stop here */
 
   blt  a0, t1, 3f
-  csrw mie, zero
+  csrw sie, zero
   wfi
 
 3:
-  /* To get g_cpu_basestack[mhartid], must get g_cpu_basestack first */
+  /* To get g_cpu_basestack[hartid], must get g_cpu_basestack first */
 
   la   t0, g_cpu_basestack
 
@@ -96,12 +126,12 @@ __start:
 
 2:
 
-  /* Disable all interrupts (i.e. timer, external) in mie */
+  /* Disable all interrupts (i.e. timer, external) in sie */
 
-	csrw	mie, zero
+  csrw	sie, zero
 
   la   t0, __trap_vec
-  csrw mtvec, t0
+  csrw stvec, t0
 
   /* Jump to qemu_rv_start */
 

arch/risc-v/src/qemu-rv/qemu_rv_irq.c

@@ -65,7 +65,7 @@ void up_irqinitialize(void)
 
   int id;
 
-  for (id = 1; id <= 52; id++)
+  for (id = 1; id <= NR_IRQS; id++)
     {
       putreg32(1, (uintptr_t)(QEMU_RV_PLIC_PRIORITY + 4 * id));
     }
@@ -150,24 +150,16 @@ void up_enable_irq(int irq)
 
   if (irq == RISCV_IRQ_SOFT)
     {
-      /* Read m/sstatus & set machine software interrupt enable in m/sie */
+      /* Read sstatus & set machine software interrupt enable in sie */
 
       SET_CSR(CSR_IE, IE_SIE);
     }
   else if (irq == RISCV_IRQ_TIMER)
     {
-      /* Read m/sstatus & set timer interrupt enable in m/sie */
+      /* Read sstatus & set timer interrupt enable in sie */
 
       SET_CSR(CSR_IE, IE_TIE);
     }
-#ifdef CONFIG_BUILD_KERNEL
-  else if (irq == RISCV_IRQ_MTIMER)
-    {
-      /* Read m/sstatus & set timer interrupt enable in m/sie */
-
-      SET_CSR(mie, MIE_MTIE);
-    }
-#endif
   else if (irq > RISCV_IRQ_EXT)
     {
       extirq = irq - RISCV_IRQ_EXT;
@@ -190,11 +182,11 @@ irqstate_t up_irq_enable(void)
 {
   irqstate_t oldstat;
 
-  /* Enable external interrupts (mie/sie) */
+  /* Enable external interrupts (sie) */
 
   SET_CSR(CSR_IE, IE_EIE);
 
-  /* Read and enable global interrupts (M/SIE) in m/sstatus */
+  /* Read and enable global interrupts (sie) in sstatus */
 
   oldstat = READ_AND_SET_CSR(CSR_STATUS, STATUS_IE);
 

arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c

@@ -39,11 +39,7 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
-#ifdef CONFIG_ARCH_RV32
-#  define RV_IRQ_MASK 27
-#else
-#  define RV_IRQ_MASK 59
-#endif
+#define RV_IRQ_MASK 59
 
 /****************************************************************************
  * Public Functions