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Debug Exception
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lupyuen committed Jul 28, 2023
1 parent 4ccd58d commit c003d2e
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Showing 3 changed files with 122 additions and 5 deletions.
9 changes: 9 additions & 0 deletions arch/risc-v/src/qemu-rv/hardware/qemu_rv_plic.h
Original file line number Diff line number Diff line change
Expand Up @@ -39,6 +39,15 @@
# define QEMU_RV_PLIC_ENABLE2 (QEMU_RV_PLIC_BASE + 0x002084)
# define QEMU_RV_PLIC_THRESHOLD (QEMU_RV_PLIC_BASE + 0x201000)
# define QEMU_RV_PLIC_CLAIM (QEMU_RV_PLIC_BASE + 0x201004)

////Testing other contexts
# define QEMU_RV_PLIC_ENABLE_CONTEXT2 (QEMU_RV_PLIC_BASE + 0x002100)
# define QEMU_RV_PLIC_ENABLE_CONTEXT3 (QEMU_RV_PLIC_BASE + 0x002180)
# define QEMU_RV_PLIC_ENABLE_CONTEXT4 (QEMU_RV_PLIC_BASE + 0x002200)
# define QEMU_RV_PLIC_ENABLE_CONTEXT5 (QEMU_RV_PLIC_BASE + 0x002280)
# define QEMU_RV_PLIC_ENABLE_CONTEXT6 (QEMU_RV_PLIC_BASE + 0x002300)
# define QEMU_RV_PLIC_ENABLE_CONTEXT7 (QEMU_RV_PLIC_BASE + 0x002380)
# define QEMU_RV_PLIC_ENABLE_CONTEXT8 (QEMU_RV_PLIC_BASE + 0x002400)
#else
# define QEMU_RV_PLIC_ENABLE1 (QEMU_RV_PLIC_BASE + 0x002000)
# define QEMU_RV_PLIC_ENABLE2 (QEMU_RV_PLIC_BASE + 0x002004)
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20 changes: 15 additions & 5 deletions arch/risc-v/src/qemu-rv/qemu_rv_irq.c
Original file line number Diff line number Diff line change
Expand Up @@ -186,13 +186,23 @@ void up_enable_irq(int irq)

if (0 <= extirq && extirq <= 63) ////TODO: Why 63?
{
////TODO: What about QEMU_RV_PLIC_ENABLE2? Why 32?
modifyreg32(QEMU_RV_PLIC_ENABLE1 + (4 * (extirq / 32)),
0, 1 << (extirq % 32));
////Testing
modifyreg32(QEMU_RV_PLIC_ENABLE2 + (4 * (extirq / 32)),////
0, 1 << (extirq % 32));////
////TODO: Test other contexts
////Test other contexts
modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT2 + (4 * (extirq / 32)),
0, 1 << (extirq % 32));
modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT3 + (4 * (extirq / 32)),
0, 1 << (extirq % 32));
modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT4 + (4 * (extirq / 32)),
0, 1 << (extirq % 32));
modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT5 + (4 * (extirq / 32)),
0, 1 << (extirq % 32));
modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT6 + (4 * (extirq / 32)),
0, 1 << (extirq % 32));
modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT7 + (4 * (extirq / 32)),
0, 1 << (extirq % 32));
modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT8 + (4 * (extirq / 32)),
0, 1 << (extirq % 32));
}
else
{
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98 changes: 98 additions & 0 deletions boards/risc-v/qemu-rv/rv-virt/scripts/ld-kernel64.script.tmp
Original file line number Diff line number Diff line change
@@ -0,0 +1,98 @@
MEMORY
{
kflash (rx) : ORIGIN = 0x40200000, LENGTH = 2048K
ksram (rwx) : ORIGIN = 0x40400000, LENGTH = 2048K
pgram (rwx) : ORIGIN = 0x40600000, LENGTH = 4096K
ramdisk (rwx) : ORIGIN = 0x40A00000, LENGTH = 16M
}
OUTPUT_ARCH("riscv")
__kflash_start = ORIGIN(kflash);
__kflash_size = LENGTH(kflash);
__ksram_start = ORIGIN(ksram);
__ksram_size = LENGTH(ksram);
__ksram_end = ORIGIN(ksram) + LENGTH(ksram);
__pgheap_start = ORIGIN(pgram);
__pgheap_size = LENGTH(pgram) + LENGTH(ramdisk);
__ramdisk_start = ORIGIN(ramdisk);
__ramdisk_size = LENGTH(ramdisk);
__ramdisk_end = ORIGIN(ramdisk) + LENGTH(ramdisk);
SECTIONS
{
. = 0x40200000;
.text :
{
_stext = . ;
*(.text)
*(.text.*)
*(.gnu.warning)
*(.stub)
*(.glue_7)
*(.glue_7t)
*(.jcr)
*(.gnu.linkonce.t.*)
*(.init)
*(.fini)
_etext = . ;
}
.rodata :
{
_srodata = . ;
*(.rodata)
*(.rodata1)
*(.rodata.*)
*(.gnu.linkonce.r*)
_erodata = . ;
}
.tdata : {
_stdata = ABSOLUTE(.);
*(.tdata .tdata.* .gnu.linkonce.td.*);
_etdata = ABSOLUTE(.);
}
.tbss : {
_stbss = ABSOLUTE(.);
*(.tbss .tbss.* .gnu.linkonce.tb.* .tcommon);
_etbss = ABSOLUTE(.);
}
_eronly = ABSOLUTE(.);
.data :
{
_sdata = . ;
*(.data)
*(.data1)
*(.data.*)
*(.gnu.linkonce.d*)
. = ALIGN(4);
_edata = . ;
}
.bss :
{
_sbss = . ;
*(.bss)
*(.bss.*)
*(.sbss)
*(.sbss.*)
*(.gnu.linkonce.b*)
*(COMMON)
_ebss = . ;
} > ksram
.pgtables (NOLOAD) : ALIGN(0x1000) {
*(.pgtables)
. = ALIGN(4);
} > ksram
.stack_top : {
. = ALIGN(32);
_ebss = ABSOLUTE(.);
} > ksram
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}

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