Fix PLIC for Hart 1 S-Mode

lupyuen2 · Jul 28, 2023 · 89d7fda · 89d7fda
1 parent c3c12d0
commit 89d7fda
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Showing 2 changed files with 22 additions and 34 deletions.
diff --git a/arch/risc-v/src/qemu-rv/hardware/qemu_rv_plic.h b/arch/risc-v/src/qemu-rv/hardware/qemu_rv_plic.h
@@ -31,25 +31,32 @@
  * Pre-processor Definitions
  ****************************************************************************/
 
+// | 0x0C00_0004 | 4B | RW | Source 1 priority
 #define QEMU_RV_PLIC_PRIORITY    (QEMU_RV_PLIC_BASE + 0x000000)
+
+// | 0x0C00_1000 | 4B | RO | Start of pending array
 #define QEMU_RV_PLIC_PENDING1    (QEMU_RV_PLIC_BASE + 0x001000)
 
+// Previously:
+// #define QEMU_RV_PLIC_PRIORITY    (QEMU_RV_PLIC_BASE + 0x000000)
+// #define QEMU_RV_PLIC_PENDING1    (QEMU_RV_PLIC_BASE + 0x001000)
+
 #ifdef CONFIG_ARCH_USE_S_MODE
-#  define QEMU_RV_PLIC_ENABLE1   (QEMU_RV_PLIC_BASE + 0x002080)
-#  define QEMU_RV_PLIC_ENABLE2   (QEMU_RV_PLIC_BASE + 0x002084)
-#  define QEMU_RV_PLIC_THRESHOLD (QEMU_RV_PLIC_BASE + 0x201000)
-#  define QEMU_RV_PLIC_CLAIM     (QEMU_RV_PLIC_BASE + 0x201004)
-
-////Testing other contexts
-#  define QEMU_RV_PLIC_ENABLE_CONTEXT0   (QEMU_RV_PLIC_BASE + 0x002000)
-#  define QEMU_RV_PLIC_ENABLE_CONTEXT1   (QEMU_RV_PLIC_BASE + 0x002080)
-#  define QEMU_RV_PLIC_ENABLE_CONTEXT2   (QEMU_RV_PLIC_BASE + 0x002100)
-#  define QEMU_RV_PLIC_ENABLE_CONTEXT3   (QEMU_RV_PLIC_BASE + 0x002180)
-#  define QEMU_RV_PLIC_ENABLE_CONTEXT4   (QEMU_RV_PLIC_BASE + 0x002200)
-#  define QEMU_RV_PLIC_ENABLE_CONTEXT5   (QEMU_RV_PLIC_BASE + 0x002280)
-#  define QEMU_RV_PLIC_ENABLE_CONTEXT6   (QEMU_RV_PLIC_BASE + 0x002300)
-#  define QEMU_RV_PLIC_ENABLE_CONTEXT7   (QEMU_RV_PLIC_BASE + 0x002380)
-#  define QEMU_RV_PLIC_ENABLE_CONTEXT8   (QEMU_RV_PLIC_BASE + 0x002400)
+// | 0x0C00_2100 | 4B | RW | Start Hart 1 S-Mode interrupt enables
+#  define QEMU_RV_PLIC_ENABLE1   (QEMU_RV_PLIC_BASE + 0x002100)
+#  define QEMU_RV_PLIC_ENABLE2   (QEMU_RV_PLIC_BASE + 0x002104)
+
+// | 0x0C20_2000 | 4B | RW | Hart 1 S-Mode priority threshold
+#  define QEMU_RV_PLIC_THRESHOLD (QEMU_RV_PLIC_BASE + 0x202000)
+
+// | 0x0C20_2004 | 4B | RW | Hart 1 S-Mode claim/complete 
+#  define QEMU_RV_PLIC_CLAIM     (QEMU_RV_PLIC_BASE + 0x202004)
+
+// Previously:
+// #  define QEMU_RV_PLIC_ENABLE1   (QEMU_RV_PLIC_BASE + 0x002080)
+// #  define QEMU_RV_PLIC_ENABLE2   (QEMU_RV_PLIC_BASE + 0x002084)
+// #  define QEMU_RV_PLIC_THRESHOLD (QEMU_RV_PLIC_BASE + 0x201000)
+// #  define QEMU_RV_PLIC_CLAIM     (QEMU_RV_PLIC_BASE + 0x201004)
 #else
 #  define QEMU_RV_PLIC_ENABLE1   (QEMU_RV_PLIC_BASE + 0x002000)
 #  define QEMU_RV_PLIC_ENABLE2   (QEMU_RV_PLIC_BASE + 0x002004)

diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_irq.c b/arch/risc-v/src/qemu-rv/qemu_rv_irq.c
@@ -188,25 +188,6 @@ void up_enable_irq(int irq)
         {
           modifyreg32(QEMU_RV_PLIC_ENABLE1 + (4 * (extirq / 32)),
                       0, 1 << (extirq % 32));
-          ////Test other contexts
-          modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT0 + (4 * (extirq / 32)),
-                      0, 1 << (extirq % 32));
-          modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT1 + (4 * (extirq / 32)),
-                      0, 1 << (extirq % 32));
-          modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT2 + (4 * (extirq / 32)),
-                      0, 1 << (extirq % 32));
-          modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT3 + (4 * (extirq / 32)),
-                      0, 1 << (extirq % 32));
-          modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT4 + (4 * (extirq / 32)),
-                      0, 1 << (extirq % 32));
-          modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT5 + (4 * (extirq / 32)),
-                      0, 1 << (extirq % 32));
-          modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT6 + (4 * (extirq / 32)),
-                      0, 1 << (extirq % 32));
-          modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT7 + (4 * (extirq / 32)),
-                      0, 1 << (extirq % 32));
-          modifyreg32(QEMU_RV_PLIC_ENABLE_CONTEXT8 + (4 * (extirq / 32)),
-                      0, 1 << (extirq % 32));
         }
       else
         {