Fixing build

arch/risc-v/include/jh7110/chip.h

@@ -0,0 +1,24 @@
+/****************************************************************************
+ * arch/risc-v/include/jh7110/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_INCLUDE_JH7110_CHIP_H
+#define __ARCH_RISCV_INCLUDE_JH7110_CHIP_H
+
+#endif /* __ARCH_RISCV_INCLUDE_JH7110_CHIP_H */

arch/risc-v/include/jh7110/irq.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/risc-v/include/qemu-rv/irq.h
+ * arch/risc-v/include/jh7110irq.h
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
@@ -18,8 +18,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_RISCV_INCLUDE_QEMU_RV_IRQ_H
-#define __ARCH_RISCV_INCLUDE_QEMU_RV_IRQ_H
+#ifndef __ARCH_RISCV_INCLUDE_JH7110IRQ_H
+#define __ARCH_RISCV_INCLUDE_JH7110IRQ_H
 
 /****************************************************************************
  * Included Files
@@ -33,4 +33,4 @@
 
 #define NR_IRQS (RISCV_IRQ_SEXT + 127)
 
-#endif /* __ARCH_RISCV_INCLUDE_QEMU_RV_IRQ_H */
+#endif /* __ARCH_RISCV_INCLUDE_JH7110IRQ_H */

arch/risc-v/src/jh7110/Make.defs

@@ -1,5 +1,5 @@
 ############################################################################
-# arch/risc-v/src/qemu-rv/Make.defs
+# arch/risc-v/src/jh7110/Make.defs
 #
 # Licensed to the Apache Software Foundation (ASF) under one or more
 # contributor license agreements.  See the NOTICE file distributed with
@@ -22,9 +22,9 @@ include common/Make.defs
 
 # Specify our HEAD assembly file.  This will be linked as
 # the first object file, so it will appear at address 0
-HEAD_ASRC = qemu_rv_head.S
+HEAD_ASRC = jh7110_head.S
 
 # Specify our C code within this directory to be included
-CHIP_CSRCS  = qemu_rv_start.c qemu_rv_irq_dispatch.c qemu_rv_irq.c
-CHIP_CSRCS += qemu_rv_timerisr.c qemu_rv_allocateheap.c
-CHIP_CSRCS += qemu_rv_mm_init.c qemu_rv_pgalloc.c
+CHIP_CSRCS  = jh7110_start.c jh7110_irq_dispatch.c jh7110_irq.c
+CHIP_CSRCS += jh7110_timerisr.c jh7110_allocateheap.c
+CHIP_CSRCS += jh7110_mm_init.c jh7110_pgalloc.c

arch/risc-v/src/jh7110/chip.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/risc-v/src/qemu-rv/chip.h
+ * arch/risc-v/src/jh7110/chip.h
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
@@ -18,21 +18,21 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_RISCV_SRC_QEMU_RV_CHIP_H
-#define __ARCH_RISCV_SRC_QEMU_RV_CHIP_H
+#ifndef __ARCH_RISCV_SRC_JH7110_CHIP_H
+#define __ARCH_RISCV_SRC_JH7110_CHIP_H
 
 /****************************************************************************
  * Included Files
  ****************************************************************************/
 
 /* Include the chip capabilities file */
 
-#include <arch/qemu-rv/chip.h>
+#include <arch/jh7110/chip.h>
 
-#include "qemu_rv_memorymap.h"
+#include "jh7110_memorymap.h"
 
-#include "hardware/qemu_rv_memorymap.h"
-#include "hardware/qemu_rv_plic.h"
+#include "hardware/jh7110_memorymap.h"
+#include "hardware/jh7110_plic.h"
 
 #include "riscv_internal.h"
 #include "riscv_percpu.h"
@@ -72,4 +72,4 @@
 #endif /* CONFIG_ARCH_INTERRUPTSTACK > 15 */
 
 #endif /* __ASSEMBLY__  */
-#endif /* __ARCH_RISCV_SRC_QEMU_RV_CHIP_H */
+#endif /* __ARCH_RISCV_SRC_JH7110_CHIP_H */

arch/risc-v/src/jh7110/hardware/jh7110_memorymap.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/risc-v/src/qemu-rv/hardware/qemu_rv_memorymap.h
+ * arch/risc-v/src/jh7110/hardware/jh7110_memorymap.h
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
@@ -18,15 +18,15 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_MEMORYMAP_H
-#define __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_MEMORYMAP_H
+#ifndef __ARCH_RISCV_SRC_JH7110_HARDWARE_JH7110_MEMORYMAP_H
+#define __ARCH_RISCV_SRC_JH7110_HARDWARE_JH7110_MEMORYMAP_H
 
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
 
 /* Register Base Address ****************************************************/
 
-#define QEMU_RV_PLIC_BASE    0x0c000000
+#define JH7110_PLIC_BASE    0x0c000000
 
-#endif /* __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_MEMORYMAP_H */
+#endif /* __ARCH_RISCV_SRC_JH7110_HARDWARE_JH7110_MEMORYMAP_H */

arch/risc-v/src/jh7110/hardware/jh7110_plic.h

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/risc-v/src/qemu-rv/hardware/qemu_rv_plic.h
+ * arch/risc-v/src/jh7110/hardware/jh7110_plic.h
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
@@ -18,8 +18,8 @@
  *
  ****************************************************************************/
 
-#ifndef __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_PLIC_H
-#define __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_PLIC_H
+#ifndef __ARCH_RISCV_SRC_JH7110_HARDWARE_JH7110_PLIC_H
+#define __ARCH_RISCV_SRC_JH7110_HARDWARE_JH7110_PLIC_H
 
 /****************************************************************************
  * Included Files
@@ -33,19 +33,19 @@
 
 /* Interrupt Priority */
 
-#define QEMU_RV_PLIC_PRIORITY    (QEMU_RV_PLIC_BASE + 0x000000)
+#define JH7110_PLIC_PRIORITY    (JH7110_PLIC_BASE + 0x000000)
 
 /* Hart 1 S-Mode Interrupt Enable */
 
-#define QEMU_RV_PLIC_ENABLE1   (QEMU_RV_PLIC_BASE + 0x002100)
-#define QEMU_RV_PLIC_ENABLE2   (QEMU_RV_PLIC_BASE + 0x002104)
+#define JH7110_PLIC_ENABLE1   (JH7110_PLIC_BASE + 0x002100)
+#define JH7110_PLIC_ENABLE2   (JH7110_PLIC_BASE + 0x002104)
 
 /* Hart 1 S-Mode Priority Threshold */
 
-#define QEMU_RV_PLIC_THRESHOLD (QEMU_RV_PLIC_BASE + 0x202000)
+#define JH7110_PLIC_THRESHOLD (JH7110_PLIC_BASE + 0x202000)
 
 /* Hart 1 S-Mode Claim / Complete */
 
-#define QEMU_RV_PLIC_CLAIM     (QEMU_RV_PLIC_BASE + 0x202004)
+#define JH7110_PLIC_CLAIM     (JH7110_PLIC_BASE + 0x202004)
 
-#endif /* __ARCH_RISCV_SRC_QEMU_RV_HARDWARE_QEMU_RV_PLIC_H */
+#endif /* __ARCH_RISCV_SRC_JH7110_HARDWARE_JH7110_PLIC_H */

arch/risc-v/src/jh7110/jh7110_allocateheap.c

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/risc-v/src/qemu-rv/qemu_rv_allocateheap.c
+ * arch/risc-v/src/jh7110/jh7110_allocateheap.c
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
@@ -102,7 +102,7 @@ void up_allocate_kheap(void **heap_start, size_t *heap_size)
   *heap_size  = usize;
 
   /* Allow user-mode access to the user heap memory in PMP
-   * is already done in qemu_rv_userspace().
+   * is already done in jh7110_userspace().
    */
 
 #else

arch/risc-v/src/jh7110/jh7110_head.S

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/risc-v/src/qemu-rv/qemu_rv_head.S
+ * arch/risc-v/src/jh7110/jh7110_head.S
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
@@ -78,7 +78,7 @@ real_start:
   /* Set stack pointer to the idle thread stack */
 
   bnez a0, 1f
-  la   sp, QEMU_RV_IDLESTACK_TOP
+  la   sp, JH7110_IDLESTACK_TOP
   j    2f
 1:
 
@@ -133,9 +133,9 @@ real_start:
   la   t0, __trap_vec
   csrw stvec, t0
 
-  /* Jump to qemu_rv_start */
+  /* Jump to jh7110_start */
 
-  jal  x1, qemu_rv_start
+  jal  x1, jh7110_start
 
   /* We shouldn't return from _start */
 

arch/risc-v/src/jh7110/jh7110_irq.c

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/risc-v/src/qemu-rv/qemu_rv_irq.c
+ * arch/risc-v/src/jh7110/jh7110_irq.c
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
@@ -51,8 +51,8 @@ void up_irqinitialize(void)
 
   /* Disable all global interrupts */
 
-  putreg32(0x0, QEMU_RV_PLIC_ENABLE1);
-  putreg32(0x0, QEMU_RV_PLIC_ENABLE2);
+  putreg32(0x0, JH7110_PLIC_ENABLE1);
+  putreg32(0x0, JH7110_PLIC_ENABLE2);
 
   /* Colorize the interrupt stack for debug purposes */
 
@@ -67,12 +67,12 @@ void up_irqinitialize(void)
 
   for (id = 1; id <= NR_IRQS; id++)
     {
-      putreg32(1, (uintptr_t)(QEMU_RV_PLIC_PRIORITY + 4 * id));
+      putreg32(1, (uintptr_t)(JH7110_PLIC_PRIORITY + 4 * id));
     }
 
   /* Set irq threshold to 0 (permits all global interrupts) */
 
-  putreg32(0, QEMU_RV_PLIC_THRESHOLD);
+  putreg32(0, JH7110_PLIC_THRESHOLD);
 
   /* Attach the common interrupt handler */
 
@@ -126,7 +126,7 @@ void up_disable_irq(int irq)
 
       if (0 <= extirq && extirq <= 63)
         {
-          modifyreg32(QEMU_RV_PLIC_ENABLE1 + (4 * (extirq / 32)),
+          modifyreg32(JH7110_PLIC_ENABLE1 + (4 * (extirq / 32)),
                       1 << (extirq % 32), 0);
         }
       else
@@ -168,7 +168,7 @@ void up_enable_irq(int irq)
 
       if (0 <= extirq && extirq <= 63)
         {
-          modifyreg32(QEMU_RV_PLIC_ENABLE1 + (4 * (extirq / 32)),
+          modifyreg32(JH7110_PLIC_ENABLE1 + (4 * (extirq / 32)),
                       0, 1 << (extirq % 32));
         }
       else

arch/risc-v/src/jh7110/jh7110_irq_dispatch.c

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/risc-v/src/qemu-rv/qemu_rv_irq_dispatch.c
+ * arch/risc-v/src/jh7110/jh7110_irq_dispatch.c
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
@@ -32,8 +32,8 @@
 #include <sys/types.h>
 
 #include "riscv_internal.h"
-#include "hardware/qemu_rv_memorymap.h"
-#include "hardware/qemu_rv_plic.h"
+#include "hardware/jh7110_memorymap.h"
+#include "hardware/jh7110_plic.h"
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -57,7 +57,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
 
   if (RISCV_IRQ_EXT == irq)
     {
-      uintptr_t val = getreg32(QEMU_RV_PLIC_CLAIM);
+      uintptr_t val = getreg32(JH7110_PLIC_CLAIM);
 
       /* Add the value to nuttx irq which is offset to the mext */
 
@@ -77,7 +77,7 @@ void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
     {
       /* Then write PLIC_CLAIM to clear pending in PLIC */
 
-      putreg32(irq - RISCV_IRQ_EXT, QEMU_RV_PLIC_CLAIM);
+      putreg32(irq - RISCV_IRQ_EXT, JH7110_PLIC_CLAIM);
     }
 
   return regs;

arch/risc-v/src/jh7110/jh7110_memorymap.h

@@ -0,0 +1,45 @@
+/****************************************************************************
+ * arch/risc-v/src/jh7110/jh7110_memorymap.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_JH7110_JH7110_MEMORYMAP_H
+#define __ARCH_RISCV_SRC_JH7110_JH7110_MEMORYMAP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "riscv_common_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Idle thread stack starts from _ebss */
+
+#ifndef __ASSEMBLY__
+#define JH7110_IDLESTACK_BASE  (uintptr_t)_ebss
+#else
+#define JH7110_IDLESTACK_BASE  _ebss
+#endif
+
+#define JH7110_IDLESTACK_SIZE (CONFIG_IDLETHREAD_STACKSIZE & ~3)
+#define JH7110_IDLESTACK_TOP  (JH7110_IDLESTACK_BASE + JH7110_IDLESTACK_SIZE)
+
+#endif /* __ARCH_RISCV_SRC_JH7110_JH7110_MEMORYMAP_H */