Clean up

lupyuen2 · Aug 3, 2023 · 5551808 · 5551808
1 parent 7ee02d6
commit 5551808
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Showing 2 changed files with 16 additions and 16 deletions.
diff --git a/drivers/serial/uart_16550.c b/drivers/serial/uart_16550.c
@@ -52,9 +52,9 @@
 
 #ifdef CONFIG_16550_UART
 
-/***************************************************************************
+/****************************************************************************
  * Pre-processor Definitions
- ***************************************************************************/
+ ****************************************************************************/
 
 /* Timeout for UART Busy Wait, in milliseconds */
 
@@ -631,7 +631,7 @@ static inline void u16550_serialout(FAR struct u16550_s *priv, int offset,
 }
 
 #ifdef CONFIG_16550_WAIT_LCR
-/***************************************************************************
+/****************************************************************************
  * Name: u16550_wait
  *
  * Description:
@@ -644,7 +644,7 @@ static inline void u16550_serialout(FAR struct u16550_s *priv, int offset,
  * Returned Value:
  *   Zero (OK) on success; ERROR if timeout.
  *
- ***************************************************************************/
+ ****************************************************************************/
 
 static int u16550_wait(FAR struct u16550_s *priv)
 {

diff --git a/include/nuttx/serial/uart_16550.h b/include/nuttx/serial/uart_16550.h
@@ -172,18 +172,18 @@
 
 /* Register offsets *********************************************************/
 
-#define UART_RBR_INCR          0 /* (DLAB =0) Receiver Buffer Register */
-#define UART_THR_INCR          0 /* (DLAB =0) Transmit Holding Register */
-#define UART_DLL_INCR          0 /* (DLAB =1) Divisor Latch LSB */
-#define UART_DLM_INCR          1 /* (DLAB =1) Divisor Latch MSB */
-#define UART_IER_INCR          1 /* (DLAB =0) Interrupt Enable Register */
-#define UART_IIR_INCR          2 /* Interrupt ID Register */
-#define UART_FCR_INCR          2 /* FIFO Control Register */
-#define UART_LCR_INCR          3 /* Line Control Register */
-#define UART_MCR_INCR          4 /* Modem Control Register */
-#define UART_LSR_INCR          5 /* Line Status Register */
-#define UART_MSR_INCR          6 /* Modem Status Register */
-#define UART_SCR_INCR          7 /* Scratch Pad Register */
+#define UART_RBR_INCR          0  /* (DLAB =0) Receiver Buffer Register */
+#define UART_THR_INCR          0  /* (DLAB =0) Transmit Holding Register */
+#define UART_DLL_INCR          0  /* (DLAB =1) Divisor Latch LSB */
+#define UART_DLM_INCR          1  /* (DLAB =1) Divisor Latch MSB */
+#define UART_IER_INCR          1  /* (DLAB =0) Interrupt Enable Register */
+#define UART_IIR_INCR          2  /* Interrupt ID Register */
+#define UART_FCR_INCR          2  /* FIFO Control Register */
+#define UART_LCR_INCR          3  /* Line Control Register */
+#define UART_MCR_INCR          4  /* Modem Control Register */
+#define UART_LSR_INCR          5  /* Line Status Register */
+#define UART_MSR_INCR          6  /* Modem Status Register */
+#define UART_SCR_INCR          7  /* Scratch Pad Register */
 #define UART_USR_INCR          31 /* UART Status Register */
 
 #define UART_RBR_OFFSET        (CONFIG_16550_REGINCR*UART_RBR_INCR)