- 👋 Hi, I’m Leon Woestenberg, a systems architect for software, SoC, FPGA, video, edge, embedded, IoT, datacenters.
- ✨ I'm designing with C, SystemVerilog, SpinalHDL, formal verification, Vivado, Quartus, RISC-V, etc.
- 👀 I’m interested in highest throughput, ultra low latency, lowest power, algorithms and protocols.
- 🌱 I’m currently learning Scala and SpinalHDL for a large FPGA chip design.
- 💞️ I’m collaborating in open-source projects that I use (OpenEmbedded, Yocto, Linux, ChibiOS, SpinalHDL, lwIP, ...)
- 📫 How to reach me, see www.sidebranch.com.
Freelance embedded systems consultant targeting interesting projects with bare-metal, RTOS, Linux, kernels, drivers, SoC, PCI Express and FPGA technologies.
-
Sidebranch
- Switzerland
- http://www.sidebranch.com/
Popular repositories Loading
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SublimeLinter-contrib-xsvlog
SublimeLinter-contrib-xsvlog PublicThis linter plugin for SublimeLinter provides an interface to 'xvlog' (from Xilinx Vivado Simulator) for SystemVerilog linting.
Python 3
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vivado-docker
vivado-docker PublicDockerfile to build a Docker image, which can run Vivado from a Docker container.
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meta-freescale
meta-freescale PublicForked from OSSystems/meta-fsl-arm
Yoctoproject BSP layer for Freescale iMX platforms
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zcu102-blinky-yocto
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BlackwireOverview
BlackwireOverview PublicForked from FPGA-House-AG/BlackwireOverview
Blackwire overview, status, roadmap and top-level documentation.
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oe-core
oe-core PublicForked from OSSystems/oe-core
The Core OE layer (mirror for work by likewise)
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