Microprocessor without Interlocked Pipeline Stages (MIPS)

MIPS VHDL implementation for Spartan-6 FPGA using ISE.

Files

The project has simulation and required files in order to upload to the FPGA.

VHDL code

What is already implemented

Multiplexer
Sign extender
ALU
Register file
Instruction Memory
Data memory
ALU controller
Controller
Program counter adder
Program counter
Shift left

Tested

What is already tested

Multiplexer
Sign extender
ALU
Register file
Instruction Memory
Data memory
ALU controller
Controller
Program counter adder
Program counter
Shift left

What has to be done

Add
And
continue working on top level block called MIPS

Built With

ISE 14.7 Webpack - IDE
Spartan-6 - FPGA
MIPS Green Sheet - Reference Data
MIPS - Reference architecture

Author

Dugagjin Lashi

License

MIT