MIPS VHDL implementation for Spartan-6 FPGA using ISE.
The project has simulation and required files in order to upload to the FPGA.
- Multiplexer
- Sign extender
- ALU
- Register file
- Instruction Memory
- Data memory
- ALU controller
- Controller
- Program counter adder
- Program counter
- Shift left
- Multiplexer
- Sign extender
- ALU
- Register file
- Instruction Memory
- Data memory
- ALU controller
- Controller
- Program counter adder
- Program counter
- Shift left
- Add
- And
- continue working on top level block called MIPS
- ISE 14.7 Webpack - IDE
- Spartan-6 - FPGA
- MIPS Green Sheet - Reference Data
- MIPS - Reference architecture
Dugagjin Lashi
MIT