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Update FPGA firmware
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@bclswl0827
bclswl0827 committed Nov 7, 2023
1 parent 0eee198 commit eea9151
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Showing 8 changed files with 194 additions and 156 deletions.
Binary file modified KiwiSDR.rx14.wf0.bit
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Binary file modified KiwiSDR.rx3.wf3.bit
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146 changes: 85 additions & 61 deletions verilog/KiwiSDR.xc7a35t.xdc
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Original file line number Diff line number Diff line change
@@ -1,9 +1,19 @@
set_property IOSTANDARD LVCMOS33 [get_ports ADC_CLKIN]
set_property IOSTANDARD LVCMOS33 [get_ports ADC_CLKEN]
set_property IOSTANDARD LVCMOS33 [get_ports BBB_SCLK]
set_property IOSTANDARD LVCMOS33 [get_ports ADC_STENL]
set_property IOSTANDARD LVCMOS33 [get_ports ADC_STSIG]
set_property IOSTANDARD LVCMOS33 [get_ports DA_DALE]
set_property IOSTANDARD LVCMOS33 [get_ports DA_DACLK]
set_property IOSTANDARD LVCMOS33 [get_ports DA_DADAT]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_TCXO]
set_property IOSTANDARD LVCMOS33 [get_ports IF_SGN]
set_property IOSTANDARD LVCMOS33 [get_ports IF_MAG]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_ISGN]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_IMAG]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_QSGN]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_QMAG]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_GSCS]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_GSCLK]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_GSDAT]
set_property IOSTANDARD LVCMOS33 [get_ports BBB_SCLK]
set_property IOSTANDARD LVCMOS33 [get_ports {BBB_CS_N[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {BBB_CS_N[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports BBB_MISO]
Expand Down Expand Up @@ -43,50 +53,60 @@ set_property IOSTANDARD LVCMOS33 [get_ports P811]
set_property IOSTANDARD LVCMOS33 [get_ports P812]
set_property IOSTANDARD LVCMOS33 [get_ports EWP]

set_property PACKAGE_PIN E12 [get_ports ADC_CLKIN]
set_property PACKAGE_PIN A8 [get_ports ADC_CLKEN]
set_property PACKAGE_PIN D13 [get_ports BBB_SCLK]
set_property PACKAGE_PIN D4 [get_ports GPS_TCXO]
set_property PACKAGE_PIN B1 [get_ports IF_SGN]
set_property PACKAGE_PIN B2 [get_ports IF_MAG]
set_property PACKAGE_PIN P16 [get_ports {BBB_CS_N[1]}]
set_property PACKAGE_PIN N16 [get_ports {BBB_CS_N[0]}]
set_property PACKAGE_PIN M15 [get_ports BBB_MISO]
set_property PACKAGE_PIN J14 [get_ports BBB_MOSI]
set_property PACKAGE_PIN F15 [get_ports ADC_OVFL]
set_property PACKAGE_PIN E16 [get_ports {ADC_DATA[15]}]
set_property PACKAGE_PIN E15 [get_ports {ADC_DATA[14]}]
set_property PACKAGE_PIN D16 [get_ports {ADC_DATA[13]}]
set_property PACKAGE_PIN D15 [get_ports {ADC_DATA[12]}]
set_property PACKAGE_PIN C16 [get_ports {ADC_DATA[11]}]
set_property PACKAGE_PIN B16 [get_ports {ADC_DATA[10]}]
set_property PACKAGE_PIN B15 [get_ports {ADC_DATA[9]}]
set_property PACKAGE_PIN A15 [get_ports {ADC_DATA[8]}]
set_property PACKAGE_PIN B14 [get_ports {ADC_DATA[7]}]
set_property PACKAGE_PIN A14 [get_ports {ADC_DATA[6]}]
set_property PACKAGE_PIN C13 [get_ports {ADC_DATA[5]}]
set_property PACKAGE_PIN A13 [get_ports {ADC_DATA[4]}]
set_property PACKAGE_PIN B12 [get_ports {ADC_DATA[3]}]
set_property PACKAGE_PIN A12 [get_ports {ADC_DATA[2]}]
set_property PACKAGE_PIN B11 [get_ports {ADC_DATA[1]}]
set_property PACKAGE_PIN A10 [get_ports {ADC_DATA[0]}]
set_property PACKAGE_PIN K16 [get_ports P926]
set_property PACKAGE_PIN K15 [get_ports SND_INTR]
set_property PACKAGE_PIN M16 [get_ports CMD_READY]
set_property PACKAGE_PIN P15 [get_ports P915]
set_property PACKAGE_PIN R16 [get_ports P913]
set_property PACKAGE_PIN R15 [get_ports P911]
set_property PACKAGE_PIN L5 [get_ports P826] ; # G129
set_property PACKAGE_PIN L4 [get_ports P819] ; # G022
set_property PACKAGE_PIN M2 [get_ports P817] ; # G027
set_property PACKAGE_PIN M1 [get_ports P818] ; # G201
set_property PACKAGE_PIN N2 [get_ports P815] ; # G115
set_property PACKAGE_PIN N1 [get_ports P816] ; # G114
set_property PACKAGE_PIN N3 [get_ports P813] ; # G023
set_property PACKAGE_PIN P1 [get_ports P814] ; # G026
set_property PACKAGE_PIN R1 [get_ports P811] ; # G113
set_property PACKAGE_PIN R2 [get_ports P812] ; # G112
set_property PACKAGE_PIN H1 [get_ports EWP]
set_property PACKAGE_PIN K18 [get_ports ADC_CLKIN]
set_property PACKAGE_PIN G15 [get_ports ADC_CLKEN]
set_property PACKAGE_PIN F15 [get_ports ADC_STENL]
set_property PACKAGE_PIN F14 [get_ports ADC_STSIG]
set_property PACKAGE_PIN F16 [get_ports DA_DALE]
set_property PACKAGE_PIN E17 [get_ports DA_DACLK]
set_property PACKAGE_PIN E13 [get_ports DA_DADAT]
set_property PACKAGE_PIN H4 [get_ports GPS_TCXO]
set_property PACKAGE_PIN J2 [get_ports GPS_ISGN]
set_property PACKAGE_PIN H2 [get_ports GPS_IMAG]
set_property PACKAGE_PIN E14 [get_ports GPS_QSGN]
set_property PACKAGE_PIN E16 [get_ports GPS_QMAG]
set_property PACKAGE_PIN D16 [get_ports GPS_GSCS]
set_property PACKAGE_PIN D14 [get_ports GPS_GSCLK]
set_property PACKAGE_PIN B15 [get_ports GPS_GSDAT]
set_property PACKAGE_PIN J19 [get_ports BBB_SCLK]
set_property PACKAGE_PIN AA21 [get_ports {BBB_CS_N[1]}]
set_property PACKAGE_PIN W22 [get_ports {BBB_CS_N[0]}]
set_property PACKAGE_PIN V22 [get_ports BBB_MISO]
set_property PACKAGE_PIN R22 [get_ports BBB_MOSI]
set_property PACKAGE_PIN N20 [get_ports ADC_OVFL]
set_property PACKAGE_PIN N18 [get_ports {ADC_DATA[15]}]
set_property PACKAGE_PIN M20 [get_ports {ADC_DATA[14]}]
set_property PACKAGE_PIN N19 [get_ports {ADC_DATA[13]}]
set_property PACKAGE_PIN M22 [get_ports {ADC_DATA[12]}]
set_property PACKAGE_PIN M21 [get_ports {ADC_DATA[11]}]
set_property PACKAGE_PIN L21 [get_ports {ADC_DATA[10]}]
set_property PACKAGE_PIN K21 [get_ports {ADC_DATA[9]}]
set_property PACKAGE_PIN K22 [get_ports {ADC_DATA[8]}]
set_property PACKAGE_PIN G20 [get_ports {ADC_DATA[7]}]
set_property PACKAGE_PIN H22 [get_ports {ADC_DATA[6]}]
set_property PACKAGE_PIN H19 [get_ports {ADC_DATA[5]}]
set_property PACKAGE_PIN J22 [get_ports {ADC_DATA[4]}]
set_property PACKAGE_PIN J15 [get_ports {ADC_DATA[3]}]
set_property PACKAGE_PIN H15 [get_ports {ADC_DATA[2]}]
set_property PACKAGE_PIN G18 [get_ports {ADC_DATA[1]}]
set_property PACKAGE_PIN H14 [get_ports {ADC_DATA[0]}]
set_property PACKAGE_PIN R21 [get_ports P926]
set_property PACKAGE_PIN P21 [get_ports SND_INTR]
set_property PACKAGE_PIN W21 [get_ports CMD_READY]
set_property PACKAGE_PIN AA20 [get_ports P915]
set_property PACKAGE_PIN Y22 [get_ports P913]
set_property PACKAGE_PIN Y21 [get_ports P911]
set_property PACKAGE_PIN T3 [get_ports P826] ; # G129
set_property PACKAGE_PIN T1 [get_ports P819] ; # G022
set_property PACKAGE_PIN U2 [get_ports P817] ; # G027
set_property PACKAGE_PIN V2 [get_ports P818] ; # G201
set_property PACKAGE_PIN R2 [get_ports P815] ; # G115
set_property PACKAGE_PIN W2 [get_ports P816] ; # G114
set_property PACKAGE_PIN R3 [get_ports P813] ; # G023
set_property PACKAGE_PIN Y2 [get_ports P814] ; # G026
set_property PACKAGE_PIN AB1 [get_ports P811] ; # G113
set_property PACKAGE_PIN AA1 [get_ports P812] ; # G112
set_property PACKAGE_PIN P1 [get_ports EWP]

# outputs
set_property DRIVE 4 [all_outputs]
Expand All @@ -96,25 +116,29 @@ set_property OFFCHIP_TERM NONE [all_outputs]
# in Vivado for power analysis only
set_load 6.000 [all_outputs]

# 100 MHz
create_clock -period 10 -name BBB_SCLK -waveform {0.000 5.00} [get_ports BBB_SCLK]
# 48 MHz
create_clock -period 20.833 -name BBB_SCLK -waveform {0.000 10.416} [get_ports BBB_SCLK]

# 16.368 MHz
create_clock -period 61.095 -name GPS_TCXO -waveform {0.000 30.548} [get_ports GPS_TCXO]

# 125 MHz
create_clock -period 8.000 -name ADC_CLKIN -waveform {0.000 4.000} [get_ports ADC_CLKIN]
# 66.666666 & 66.666600 MHz
create_clock -period 15.000 -name ADC_CLKIN -waveform {0.000 7.500} [get_ports ADC_CLKIN]

set_input_delay -clock [get_clocks ADC_CLKIN] -min -add_delay 1.300 [get_ports {ADC_DATA[*]}]
set_input_delay -clock [get_clocks ADC_CLKIN] -max -add_delay 4.000 [get_ports {ADC_DATA[*]}]
set_input_delay -clock [get_clocks ADC_CLKIN] -min -add_delay 1.300 [get_ports ADC_OVFL]
set_input_delay -clock [get_clocks ADC_CLKIN] -max -add_delay 4.000 [get_ports ADC_OVFL]
set_input_delay -clock [get_clocks BBB_SCLK] -min -add_delay 4.000 [get_ports BBB_MOSI]
set_input_delay -clock [get_clocks BBB_SCLK] -max -add_delay 8.000 [get_ports BBB_MOSI]
set_input_delay -clock [get_clocks GPS_TCXO] -min -add_delay 10.000 [get_ports IF_SGN]
set_input_delay -clock [get_clocks GPS_TCXO] -max -add_delay 54.095 [get_ports IF_SGN] ; # gives Tsetup=7ns
set_input_delay -clock [get_clocks GPS_TCXO] -min -add_delay 10.000 [get_ports IF_MAG]
set_input_delay -clock [get_clocks GPS_TCXO] -max -add_delay 54.095 [get_ports IF_MAG]
set_input_delay -clock [get_clocks ADC_CLKIN] -min -add_delay 1.400 [get_ports {ADC_DATA[*]}]
set_input_delay -clock [get_clocks ADC_CLKIN] -max -add_delay 5.400 [get_ports {ADC_DATA[*]}]
set_input_delay -clock [get_clocks ADC_CLKIN] -min -add_delay 1.400 [get_ports ADC_OVFL]
set_input_delay -clock [get_clocks ADC_CLKIN] -max -add_delay 5.400 [get_ports ADC_OVFL]
set_input_delay -clock [get_clocks BBB_SCLK] -min -add_delay 6.846 [get_ports BBB_MOSI]
set_input_delay -clock [get_clocks BBB_SCLK] -max -add_delay 17.263 [get_ports BBB_MOSI]
set_input_delay -clock [get_clocks GPS_TCXO] -min -add_delay 10.000 [get_ports GPS_ISGN]
set_input_delay -clock [get_clocks GPS_TCXO] -max -add_delay 54.095 [get_ports GPS_ISGN] ; # gives Tsetup=7ns
set_input_delay -clock [get_clocks GPS_TCXO] -min -add_delay 10.000 [get_ports GPS_IMAG]
set_input_delay -clock [get_clocks GPS_TCXO] -max -add_delay 54.095 [get_ports GPS_IMAG]
set_input_delay -clock [get_clocks GPS_TCXO] -min -add_delay 10.000 [get_ports GPS_QSGN]
set_input_delay -clock [get_clocks GPS_TCXO] -max -add_delay 54.095 [get_ports GPS_QSGN]
set_input_delay -clock [get_clocks GPS_TCXO] -min -add_delay 10.000 [get_ports GPS_QMAG]
set_input_delay -clock [get_clocks GPS_TCXO] -max -add_delay 54.095 [get_ports GPS_QMAG]

# FIXME: is MISO timing marginal?
set_output_delay -clock [get_clocks BBB_SCLK] -max -add_delay 2.290 [get_ports BBB_MISO]
Expand Down
144 changes: 77 additions & 67 deletions verilog/KiwiSDR.xdc
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Original file line number Diff line number Diff line change
@@ -1,9 +1,19 @@
set_property IOSTANDARD LVCMOS33 [get_ports ADC_CLKIN]
set_property IOSTANDARD LVCMOS33 [get_ports ADC_CLKEN]
set_property IOSTANDARD LVCMOS33 [get_ports BBB_SCLK]
set_property IOSTANDARD LVCMOS33 [get_ports ADC_STENL]
set_property IOSTANDARD LVCMOS33 [get_ports ADC_STSIG]
set_property IOSTANDARD LVCMOS33 [get_ports DA_DALE]
set_property IOSTANDARD LVCMOS33 [get_ports DA_DACLK]
set_property IOSTANDARD LVCMOS33 [get_ports DA_DADAT]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_TCXO]
set_property IOSTANDARD LVCMOS33 [get_ports IF_SGN]
set_property IOSTANDARD LVCMOS33 [get_ports IF_MAG]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_ISGN]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_IMAG]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_QSGN]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_QMAG]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_GSCS]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_GSCLK]
set_property IOSTANDARD LVCMOS33 [get_ports GPS_GSDAT]
set_property IOSTANDARD LVCMOS33 [get_ports BBB_SCLK]
set_property IOSTANDARD LVCMOS33 [get_ports {BBB_CS_N[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {BBB_CS_N[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports BBB_MISO]
Expand Down Expand Up @@ -43,60 +53,60 @@ set_property IOSTANDARD LVCMOS33 [get_ports P811]
set_property IOSTANDARD LVCMOS33 [get_ports P812]
set_property IOSTANDARD LVCMOS33 [get_ports EWP]

set_property PACKAGE_PIN E12 [get_ports ADC_CLKIN]
set_property PACKAGE_PIN A8 [get_ports ADC_CLKEN]
set_property PACKAGE_PIN A2 [get_ports ADC_STENL]
set_property PACKAGE_PIN A3 [get_ports ADC_STSIG]
set_property PACKAGE_PIN A7 [get_ports DA_DALE]
set_property PACKAGE_PIN A5 [get_ports DA_DACLK]
set_property PACKAGE_PIN A4 [get_ports DA_DADAT]
set_property PACKAGE_PIN D4 [get_ports GPS_TCXO]
set_property PACKAGE_PIN B1 [get_ports GPS_ISGN]
set_property PACKAGE_PIN B2 [get_ports GPS_IMAG]
set_property PACKAGE_PIN E1 [get_ports GPS_QSGN]
set_property PACKAGE_PIN D1 [get_ports GPS_QMAG]
set_property PACKAGE_PIN C1 [get_ports GPS_GSCS]
set_property PACKAGE_PIN G2 [get_ports GPS_GSCLK]
set_property PACKAGE_PIN G1 [get_ports GPS_GSDAT]
set_property PACKAGE_PIN D13 [get_ports BBB_SCLK]
set_property PACKAGE_PIN P16 [get_ports {BBB_CS_N[1]}]
set_property PACKAGE_PIN N16 [get_ports {BBB_CS_N[0]}]
set_property PACKAGE_PIN M15 [get_ports BBB_MISO]
set_property PACKAGE_PIN J14 [get_ports BBB_MOSI]
set_property PACKAGE_PIN F15 [get_ports ADC_OVFL]
set_property PACKAGE_PIN E16 [get_ports {ADC_DATA[15]}]
set_property PACKAGE_PIN E15 [get_ports {ADC_DATA[14]}]
set_property PACKAGE_PIN D16 [get_ports {ADC_DATA[13]}]
set_property PACKAGE_PIN D15 [get_ports {ADC_DATA[12]}]
set_property PACKAGE_PIN C16 [get_ports {ADC_DATA[11]}]
set_property PACKAGE_PIN B16 [get_ports {ADC_DATA[10]}]
set_property PACKAGE_PIN B15 [get_ports {ADC_DATA[9]}]
set_property PACKAGE_PIN A15 [get_ports {ADC_DATA[8]}]
set_property PACKAGE_PIN B14 [get_ports {ADC_DATA[7]}]
set_property PACKAGE_PIN A14 [get_ports {ADC_DATA[6]}]
set_property PACKAGE_PIN C13 [get_ports {ADC_DATA[5]}]
set_property PACKAGE_PIN A13 [get_ports {ADC_DATA[4]}]
set_property PACKAGE_PIN B12 [get_ports {ADC_DATA[3]}]
set_property PACKAGE_PIN A12 [get_ports {ADC_DATA[2]}]
set_property PACKAGE_PIN B11 [get_ports {ADC_DATA[1]}]
set_property PACKAGE_PIN A10 [get_ports {ADC_DATA[0]}]
set_property PACKAGE_PIN K16 [get_ports P926]
set_property PACKAGE_PIN K15 [get_ports SND_INTR]
set_property PACKAGE_PIN M16 [get_ports CMD_READY]
set_property PACKAGE_PIN P15 [get_ports P915]
set_property PACKAGE_PIN R16 [get_ports P913]
set_property PACKAGE_PIN R15 [get_ports P911]
set_property PACKAGE_PIN L5 [get_ports P826] ; # G129
set_property PACKAGE_PIN L4 [get_ports P819] ; # G022
set_property PACKAGE_PIN M2 [get_ports P817] ; # G027
set_property PACKAGE_PIN M1 [get_ports P818] ; # G201
set_property PACKAGE_PIN N2 [get_ports P815] ; # G115
set_property PACKAGE_PIN N1 [get_ports P816] ; # G114
set_property PACKAGE_PIN N3 [get_ports P813] ; # G023
set_property PACKAGE_PIN P1 [get_ports P814] ; # G026
set_property PACKAGE_PIN R1 [get_ports P811] ; # G113
set_property PACKAGE_PIN R2 [get_ports P812] ; # G112
set_property PACKAGE_PIN H1 [get_ports EWP]
set_property PACKAGE_PIN K18 [get_ports ADC_CLKIN]
set_property PACKAGE_PIN G15 [get_ports ADC_CLKEN]
set_property PACKAGE_PIN F15 [get_ports ADC_STENL]
set_property PACKAGE_PIN F14 [get_ports ADC_STSIG]
set_property PACKAGE_PIN F16 [get_ports DA_DALE]
set_property PACKAGE_PIN E17 [get_ports DA_DACLK]
set_property PACKAGE_PIN E13 [get_ports DA_DADAT]
set_property PACKAGE_PIN H4 [get_ports GPS_TCXO]
set_property PACKAGE_PIN J2 [get_ports GPS_ISGN]
set_property PACKAGE_PIN H2 [get_ports GPS_IMAG]
set_property PACKAGE_PIN E14 [get_ports GPS_QSGN]
set_property PACKAGE_PIN E16 [get_ports GPS_QMAG]
set_property PACKAGE_PIN D16 [get_ports GPS_GSCS]
set_property PACKAGE_PIN D14 [get_ports GPS_GSCLK]
set_property PACKAGE_PIN B15 [get_ports GPS_GSDAT]
set_property PACKAGE_PIN J19 [get_ports BBB_SCLK]
set_property PACKAGE_PIN AA21 [get_ports {BBB_CS_N[1]}]
set_property PACKAGE_PIN W22 [get_ports {BBB_CS_N[0]}]
set_property PACKAGE_PIN V22 [get_ports BBB_MISO]
set_property PACKAGE_PIN R22 [get_ports BBB_MOSI]
set_property PACKAGE_PIN N20 [get_ports ADC_OVFL]
set_property PACKAGE_PIN N18 [get_ports {ADC_DATA[15]}]
set_property PACKAGE_PIN M20 [get_ports {ADC_DATA[14]}]
set_property PACKAGE_PIN N19 [get_ports {ADC_DATA[13]}]
set_property PACKAGE_PIN M22 [get_ports {ADC_DATA[12]}]
set_property PACKAGE_PIN M21 [get_ports {ADC_DATA[11]}]
set_property PACKAGE_PIN L21 [get_ports {ADC_DATA[10]}]
set_property PACKAGE_PIN K21 [get_ports {ADC_DATA[9]}]
set_property PACKAGE_PIN K22 [get_ports {ADC_DATA[8]}]
set_property PACKAGE_PIN G20 [get_ports {ADC_DATA[7]}]
set_property PACKAGE_PIN H22 [get_ports {ADC_DATA[6]}]
set_property PACKAGE_PIN H19 [get_ports {ADC_DATA[5]}]
set_property PACKAGE_PIN J22 [get_ports {ADC_DATA[4]}]
set_property PACKAGE_PIN J15 [get_ports {ADC_DATA[3]}]
set_property PACKAGE_PIN H15 [get_ports {ADC_DATA[2]}]
set_property PACKAGE_PIN G18 [get_ports {ADC_DATA[1]}]
set_property PACKAGE_PIN H14 [get_ports {ADC_DATA[0]}]
set_property PACKAGE_PIN R21 [get_ports P926]
set_property PACKAGE_PIN P21 [get_ports SND_INTR]
set_property PACKAGE_PIN W21 [get_ports CMD_READY]
set_property PACKAGE_PIN AA20 [get_ports P915]
set_property PACKAGE_PIN Y22 [get_ports P913]
set_property PACKAGE_PIN Y21 [get_ports P911]
set_property PACKAGE_PIN T3 [get_ports P826] ; # G129
set_property PACKAGE_PIN T1 [get_ports P819] ; # G022
set_property PACKAGE_PIN U2 [get_ports P817] ; # G027
set_property PACKAGE_PIN V2 [get_ports P818] ; # G201
set_property PACKAGE_PIN R2 [get_ports P815] ; # G115
set_property PACKAGE_PIN W2 [get_ports P816] ; # G114
set_property PACKAGE_PIN R3 [get_ports P813] ; # G023
set_property PACKAGE_PIN Y2 [get_ports P814] ; # G026
set_property PACKAGE_PIN AB1 [get_ports P811] ; # G113
set_property PACKAGE_PIN AA1 [get_ports P812] ; # G112
set_property PACKAGE_PIN P1 [get_ports EWP]

# outputs
set_property DRIVE 4 [all_outputs]
Expand All @@ -106,21 +116,21 @@ set_property OFFCHIP_TERM NONE [all_outputs]
# in Vivado for power analysis only
set_load 6.000 [all_outputs]

# 100 MHz
create_clock -period 10 -name BBB_SCLK -waveform {0.000 5.00} [get_ports BBB_SCLK]
# 48 MHz
create_clock -period 20.833 -name BBB_SCLK -waveform {0.000 10.416} [get_ports BBB_SCLK]

# 16.368 MHz
create_clock -period 61.095 -name GPS_TCXO -waveform {0.000 30.548} [get_ports GPS_TCXO]

# 125 MHz
create_clock -period 8.000 -name ADC_CLKIN -waveform {0.000 4.000} [get_ports ADC_CLKIN]
# 66.666666 & 66.666600 MHz
create_clock -period 15.000 -name ADC_CLKIN -waveform {0.000 7.500} [get_ports ADC_CLKIN]

set_input_delay -clock [get_clocks ADC_CLKIN] -min -add_delay 1.300 [get_ports {ADC_DATA[*]}]
set_input_delay -clock [get_clocks ADC_CLKIN] -max -add_delay 4.000 [get_ports {ADC_DATA[*]}]
set_input_delay -clock [get_clocks ADC_CLKIN] -min -add_delay 1.300 [get_ports ADC_OVFL]
set_input_delay -clock [get_clocks ADC_CLKIN] -max -add_delay 4.000 [get_ports ADC_OVFL]
set_input_delay -clock [get_clocks BBB_SCLK] -min -add_delay 4.000 [get_ports BBB_MOSI]
set_input_delay -clock [get_clocks BBB_SCLK] -max -add_delay 8.000 [get_ports BBB_MOSI]
set_input_delay -clock [get_clocks ADC_CLKIN] -min -add_delay 1.400 [get_ports {ADC_DATA[*]}]
set_input_delay -clock [get_clocks ADC_CLKIN] -max -add_delay 5.400 [get_ports {ADC_DATA[*]}]
set_input_delay -clock [get_clocks ADC_CLKIN] -min -add_delay 1.400 [get_ports ADC_OVFL]
set_input_delay -clock [get_clocks ADC_CLKIN] -max -add_delay 5.400 [get_ports ADC_OVFL]
set_input_delay -clock [get_clocks BBB_SCLK] -min -add_delay 6.846 [get_ports BBB_MOSI]
set_input_delay -clock [get_clocks BBB_SCLK] -max -add_delay 17.263 [get_ports BBB_MOSI]
set_input_delay -clock [get_clocks GPS_TCXO] -min -add_delay 10.000 [get_ports GPS_ISGN]
set_input_delay -clock [get_clocks GPS_TCXO] -max -add_delay 54.095 [get_ports GPS_ISGN] ; # gives Tsetup=7ns
set_input_delay -clock [get_clocks GPS_TCXO] -min -add_delay 10.000 [get_ports GPS_IMAG]
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8 changes: 1 addition & 7 deletions verilog/kiwi.cfg.vh
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,2 @@
localparam RX_CFG = 4; // Available values: 4, 3, 8, 14
localparam RX_CFG = 4;
`define USE_WF

// In case RX_CFG is set to 4, the generated bitstream should be named KiwiSDR.rx4.wf4.bit
// In case RX_CFG is set to 3, the generated bitstream should be named KiwiSDR.rx3.wf3.bit
// In case RX_CFG is set to 8, the generated bitstream should be named KiwiSDR.rx8.wf2.bit
// In case RX_CFG is set to 14, the generated bitstream should be named KiwiSDR.rx14.wf0.bit
// Remove `define USE_WF when RX_CFG is set to 14
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