Xtensa patches (17.x) (Do not merge, PR created for easier review only) #86

gerekon · 2023-12-28T11:21:49Z

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Initial codegen support for simple ALU operations.

Constant Pool.

operations. Lower ConstantPool, GlobalAddress, BlockAddress and JumpTable. Implement lowering of External and JumpTable symbols to MCInst representation.

Implement lowering of dynamic_stackalloc, stacksave, stackrestore.

constructs.

Also lower SHL, SRA, SRL with register operands.

patterns. Implement load unsigned 8-bit pseudo operation. Implement extending loads patterns extloadi1/i8/i16.

Add support for llvm.{frameaddress,returnaddress} intrinsics.

Implement volatile load/store from/to volatile memory location.

scavenger. Reserve an emergency spill slot for the register scavenger when Windowed Call ABI is used.

Also implement User Registers class.

SELECT_CC/SETCC/BR_CC. Implement DAG Combine for BRCOND operation with f32 operands.

operations.

This option is passed to GNU AS and makes Xtensa compiler driver compatible with GCC.

Intrinsics: __builtin_xtensa_ae_int32x2 and builtin_xtensa_int32 are convenience functions for easy integer-vector and vector-vector conversions that conform to Xtensa coding style. Xtensa C dialect allows for implicit conversion between wider and narrower vector (via shuffle) and between integer and any vector (via broadcast). Standard Clang vectors do not support this, so these functions provide a handicap for better portability.

…attribute__((near))`

…sif toolchain This reverts commit 9e09569. This reverts commit 127d475. This reverts commit 4fa8704. This reverts commit 70cba36.

Fix disassembling of the Imm8_sh8, Imm64n_4n, Offset8m32, Entry_Imm12 immedaite operands.

andreisfr added 30 commits September 29, 2023 02:31

[Xtensa] Initial support of the ALU operations.

041c8e8

Initial codegen support for simple ALU operations.

[Xtensa] Codegen support for memory operations

54e52dc

[Xtensa] Add Constant Pool

609c113

[Xtensa] Implement assembler representation of the

97bf10f

Constant Pool.

[Xtensa] Implement lowering constants.

b5e0e97

[Xtensa] Add support of the Xtensa function calls

8d0ed4a

[Xtensa] Implement lowering ConstantPool and address

91c5c2f

operations. Lower ConstantPool, GlobalAddress, BlockAddress and JumpTable. Implement lowering of External and JumpTable symbols to MCInst representation.

[Xtensa] Implement emitPrologue/emitEpilogue

d50e16c

[Xtensa] Lower stack operations

8e1f1e0

Implement lowering of dynamic_stackalloc, stacksave, stackrestore.

[Xtensa] Implement lowering SELECT_CC, SETCC

0ca4ba0

[Xtensa] Support for a variety of additional LLVM IR

2a616bb

constructs.

[Xtensa] Lower SHIFT PARTS and shift operations.

300d6d1

Also lower SHL, SRA, SRL with register operands.

[Xtensa] Implement load pseudo operations and

307e063

patterns. Implement load unsigned 8-bit pseudo operation. Implement extending loads patterns extloadi1/i8/i16.

[Xtensa] Support for variable arguments

6dd43f9

[Xtensa] Implement lowering BR_JT operation

8385d12

[Xtensa] Support for address intrinsics.

a606fba

Add support for llvm.{frameaddress,returnaddress} intrinsics.

[Xtensa] Add basic support for inline asm constraints

b7768c6

[Xtensa] Implement volatile load/store.

231bfaf

Implement volatile load/store from/to volatile memory location.

[Xtensa] Implement branch analysis

e371291

[Xtensa] Implement support for the BranchRelaxation

5ab25a0

[Xtensa] Implement code density feature operations

19b4d5e

[Xtensa] Add code size reduction pass.

58ce46f

[Xtensa] Implement Windowed feature operations

f169f0f

[Xtensa] Implement Windowed Call ABI

94e0e70

[Xtensa] Reserve an emergency spill slot for

e4e6dd0

scavenger. Reserve an emergency spill slot for the register scavenger when Windowed Call ABI is used.

[Xtensa] Implement Boolean feature operations

37613b6

[Xtensa] Implement Floating-Point feature operations.

c6de0ed

Also implement User Registers class.

[Xtensa] Lowering Floating-Point Operations

46eb6b0

SELECT_CC/SETCC/BR_CC. Implement DAG Combine for BRCOND operation with f32 operands.

[Xtensa] Implement DAG Combine for FADD and FSUB

4402d36

operations.

[Xtensa] Implement Loop, SEXT and NSA features.

6aca4dc

maciej-czekaj and others added 29 commits January 23, 2024 23:26

[Xtensa] Support bit vectors in BRegFixupPass

051d9d8

[Xtensa] Add codegen tests for bit vectors

5132ec1

[Xtensa] Remove unsspported intrinsic xt_conjc_s

2ad4d80

[Xtensa] Add HIFI3 intrinsic definitions to clang

09d8002

[Xtensa] Add constant checks for HIFI3 intrinsics

15f576e

[Xtensa] Support HIFI3 vectors in LLVM calls

de014b3

[Xtensa] Add HIFI3 intrinsics to Clang codegen

97b2e98

[Xtensa] Fix xt_lsxp builtin definition

6788c12

[Xtensa] Support bool vectors in LLVM calls

13128fc

[Xtensa] Add --text-section-literals option

9ef315c

This option is passed to GNU AS and makes Xtensa compiler driver compatible with GCC.

[Xtensa] Add HIFI3 C types and intrinsics

ece6ae3

[Xtensa] Add support for decoding from HIFI namespace

2bace8a

[Xtensa] Implement support for __attribute__((short__call)) and `__…

df27f60

…attribute__((near))`

[RISCV] Add 'tcontrol' CSR register

5c0f2a6

[Toolchain][RISCV][Xtensa] Add Espressif baremetal toolchain

461f7b6

[Toolchain][RISCV][Xtensa] Remove GCC installation support for Espres…

7f9ce3f

…sif toolchain This reverts commit 9e09569. This reverts commit 127d475. This reverts commit 4fa8704. This reverts commit 70cba36.

[Clang] Fix undefined std::errc for MinGW build

066dea0

[LLD] Disable x86_64 specific test if target is no enabled

5c7a276

esp/ci: Use CMake-based build scripts

c9f9f25

[Xtensa] Fix disassembler.

387621f

Fix disassembling of the Imm8_sh8, Imm64n_4n, Offset8m32, Entry_Imm12 immedaite operands.

[Xtensa] Add predefined macros for core configuration

c62f55b

[Clang] Add stdint preprocessor tests for Xtensa

4b9eb0b

[LLVM][Xtensa] Remove DFP accelrator feature from ESP32-S3

69c9c7c

[Clang][Xtensa] Add tests for core config pre-defined macros

d1d105a

esp/ci: Upgrade GCC toolchain components version to '13.2.0_20240305'

e6e27d9

[Toolchain][Espressif] Use custom prefixes for 'as' and 'ld'

7b22210

esp:/ci: Switch to combined all-in-one toolchain

b02b417

[Xtensa] Fix issue with adding scavenging frame index

829c5ad

gerekon closed this May 8, 2024

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Xtensa patches (17.x) (Do not merge, PR created for easier review only) #86

Xtensa patches (17.x) (Do not merge, PR created for easier review only) #86

gerekon commented Dec 28, 2023

Xtensa patches (17.x) (Do not merge, PR created for easier review only) #86

Xtensa patches (17.x) (Do not merge, PR created for easier review only) #86

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gerekon commented Dec 28, 2023