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esp-rs · Nov 4, 2024 · 7d3592c · 7d3592c
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commit 7d3592c
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Showing 5 changed files with 9 additions and 17 deletions.
diff --git a/esp-hal/Cargo.toml b/esp-hal/Cargo.toml
@@ -55,13 +55,13 @@ xtensa-lx                = { version = "0.9.0", optional = true }
 # IMPORTANT:
 # Each supported device MUST have its PAC included below along with a
 # corresponding feature.
-esp32   = { version = "0.33.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true }
-esp32c2 = { version = "0.22.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true }
-esp32c3 = { version = "0.25.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true }
-esp32c6 = { version = "0.16.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true }
-esp32h2 = { version = "0.12.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true }
-esp32s2 = { version = "0.24.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true }
-esp32s3 = { version = "0.28.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "390c88b", features = ["critical-section", "rt"], optional = true }
+esp32   = { version = "0.33.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "80ed3b5", features = ["critical-section", "rt"], optional = true }
+esp32c2 = { version = "0.22.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "80ed3b5", features = ["critical-section", "rt"], optional = true }
+esp32c3 = { version = "0.25.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "80ed3b5", features = ["critical-section", "rt"], optional = true }
+esp32c6 = { version = "0.16.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "80ed3b5", features = ["critical-section", "rt"], optional = true }
+esp32h2 = { version = "0.12.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "80ed3b5", features = ["critical-section", "rt"], optional = true }
+esp32s2 = { version = "0.24.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "80ed3b5", features = ["critical-section", "rt"], optional = true }
+esp32s3 = { version = "0.28.0", git = "https://github.com/esp-rs/esp-pacs.git", rev = "80ed3b5", features = ["critical-section", "rt"], optional = true }
 
 [target.'cfg(target_arch = "riscv32")'.dependencies]
 esp-riscv-rt = { version = "0.9.0", path = "../esp-riscv-rt" }

diff --git a/esp-hal/src/uart.rs b/esp-hal/src/uart.rs
@@ -758,7 +758,7 @@ where
             cfg_if::cfg_if! {
                 if #[cfg(esp32)] {
                     // https://docs.espressif.com/projects/esp-chip-errata/en/latest/esp32/03-errata-description/esp32/cpu-subsequent-access-halted-when-get-interrupted.html
-                    xtensa_lx::interrupt::free(|_| {
+                    xtensa_lx::interrupt::free(|| {
                         *byte = fifo.read().rxfifo_rd_byte().bits();
                     });
                 } else {

diff --git a/examples/Cargo.toml b/examples/Cargo.toml
@@ -73,7 +73,3 @@ overflow-checks  = false
 
 [patch.crates-io]
 xtensa-lx = { path = "../xtensa-lx" }
-xtensa-lx-rt = { path = "../xtensa-lx-rt" }
-esp32 = { git = "https://github.com/esp-rs/esp-pacs", branch = "spin" }
-esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", branch = "spin" }
-esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", branch = "spin" }
diff --git a/hil-test/Cargo.toml b/hil-test/Cargo.toml
@@ -315,7 +315,3 @@ overflow-checks  = false
 
 [patch.crates-io]
 xtensa-lx = { path = "../xtensa-lx" }
-xtensa-lx-rt = { path = "../xtensa-lx-rt" }
-esp32 = { git = "https://github.com/esp-rs/esp-pacs", branch = "spin" }
-esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", branch = "spin" }
-esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", branch = "spin" }
diff --git a/xtensa-lx/src/interrupt.rs b/xtensa-lx/src/interrupt.rs
@@ -62,7 +62,7 @@ pub fn disable_mask(mask: u32) -> u32 {
     let _dummy: u32;
     unsafe {
         asm!("
-        xsr.intenable {0}  // get mask and temporarily disable interrupts 
+        xsr.intenable {0}  // get mask and temporarily disable interrupts
         and {1}, {1}, {0}
         rsync
         wsr.intenable {1}