Install GHDL and Yosys to CI to be able to simulate Microwatt/NeoRV32 with Verilator.

[enjoy-digital]

No description provided.

[mithro]

Containers with these tools are available from https://github.com/hdl/containers

We will hopefully soon have GHDL available through the conda environment provided by https://github.com/hdl/conda-eda too.

[mithro]

@umarcor, Antmicro and the BYU team has been working on making sure that the full F4PGA toolchain (with GHDL + Surelog + Yosys + VPR + nextpnr) is also easily available.

[mithro]

FYI - @kgugala / @acomodi

[umarcor]

See chipsalliance/f4pga#574 and chipsalliance/f4pga#575.

  Test-VHDL:
    runs-on: ubuntu-latest

    steps:

      - name: 🧰 Checkout
        uses: actions/checkout@v3

      - name: 🚧 GHDL synth
        run: make -C test/vhdl/counter synth

      - name: 🚧 F4PGA Action (arty_35 | vhdl/counter)
        uses: ./action
        with:
          image: xc7/a50t
          cmd: |
            cd test/vhdl/counter
            f4pga build --flow arty_35.json

      - name: '📤 Upload artifact: Arty 35 bitstream'
        uses: actions/upload-artifact@v3
        with:
          name: arty_35-Bitstream-VHDL-Counter
          path: test/vhdl/counter/top.bit

synth:
	docker run --rm \
	-v /$(shell pwd)://wrk -w //wrk \
	gcr.io/hdl-containers/ghdl \
	ghdl synth --std=08 --out=verilog counter.vhd -e Arty_Counter > top.v

[enjoy-digital]

Thanks @mithro, @umarcor. If possible, I'll have a closer look. I'm trying to have the same approach to install things on CI than on regular machine (and avoid Conda/Contrainers), so I'll try to see if I can use that.

From https://twitter.com/antonblanchard/status/1536962193627181056, it seems we'll also be able to avoid the use of Yosys in the conversion.

[umarcor]

@enjoy-digital, indeed, any installation of GHDL should handle ghdl synth --std=08 --out=verilog counter.vhd -e Arty_Counter > top.v. That's the easiest approach.

[enjoy-digital]

Thanks @umarcor. I'm not sure this was possible in the past with Microwatt, but it seems to be the case now, so will simplify the conversion flow.

[umarcor]

The flow through the ghdl-yosys-plugin was ready-to-use in early 2020 (I met Anton at ORCONF2019 and we collaborated to have the CI of microwatt use GHDL, Yosys and nextpnr), while the ghdl synth command was added in early 2021. Since many projects took Microwatt's makefile (and https://github.com/antonblanchard/ghdl-yosys-blink) as a reference, the other flow went partially unnoticed for the last year.

Nevertheless, note that the flows are not exactly equivalent. ghdl synth produces a non-optimised netlist, while yosys can run multiple stages. ghdl synth is mostly useful for linting and to work around tools with poor VHDL support.

[enjoy-digital]

Thanks a lot for the additional infos @umarcor, this helps getting the bigger picture/history of things. This could be interesting to support both flow in LiteX. Direct verilog generation through GHDL will mostly be useful for simulation of VHDL Cores/CPU (ex Microwatt, NeoRV32) and GHDL+Yosys flow for synthesis on hardware with open-source toolchains. But to be able to detect eventual issues, being able to easily switch from one to another would be convenient.

I guess the next steps will be to experiment with ghdl_synth, then integrate the VHDL -> Verilog conversion directly in the build flow and then see how to setup the CI for this.

[umarcor]

@enjoy-digital check http://ghdl.github.io/ghdl/using/Synthesis.html. Ping me if you find anything unclear.

Note that http://ghdl.github.io/ghdl/using/Synthesis.html#convert-v-hdl-to-other-formats is missing the JSON output, which can be used with netlistsvg: ghdl/ghdl#1783.

Should it be useful/inspiring:

GENERICS ?= -gWL=16 -gprec=8

SYNTH_OUT_TYPE ?= raw-vhdl
ifeq ($(SYNTH_OUT_TYPE), verilog)
SYNTH_EXT = v
else
SYNTH_EXT = vhd
endif

mkdir-synth:
	mkdir -p synth

synth-prog: mkdir-synth
	ghdl synth --std=08 \
	  --out=$(SYNTH_OUT_TYPE) \
	  $(GENERICS) \
	  ./rtl/*.vhd \
	  -e top_CRI_prog_actfunc \
	  | tee synth/top_CRI_prog_actfunc.synth.$(SYNTH_OUT_TYPE).$(SYNTH_EXT)